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Ari_C
Visitor
Visitor
312 Views
Registered: ‎06-11-2021

Get user input in Vitis

Hello,

I have created a Test Pattern Generator with a box overlay that I am programming onto an FPGA. The location and dimensions of the box are based on three constant IP blocks in the block diagram. I eventually want to have it so that instead of the three constant blocks, the location and dimensions are based upon user input instead of the constant blocks with their values defined in the Vivado Block Diagram. Would it be possible to do this?

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watari
Professor
Professor
283 Views
Registered: ‎06-16-2013

Hi @Ari_C 

 

> Would it be possible to do this?

 

Yes.

BTW, does your Test Pattern Generator have axi4lite interface ?

I guess that this answer is no. If so, I recommend to add pragma to create axi4lite interface like the following in your HLS code.

 

int example(hls::stream<ap_axis<24,1,1,1> >& m_axis,
        int v_size, int h_size
){
#pragma HLS INTERFACE s_axilite port=v_size
#pragma HLS INTERFACE s_axilite port=h_size

 

Would you try it ?

 

Best regards,

Ari_C
Visitor
Visitor
230 Views
Registered: ‎06-11-2021

Hi @watari I actually did include an axi4lite interface to my IP block since I was trying to make the ports on my block as similar to the ones on the Xilinx TPG aside from the ports for the three constants. 

my_tpg_ip_block.PNG
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