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Observer h4cks4w
Observer
7,060 Views
Registered: ‎08-16-2013

Getting from HLS RTL to implementation through a Tcl script

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I have some C code which I am running through Vivado HLS.  I can take the generated RTL and run it through a simulator and it is doing what I want it to do.  Now I would like to build a bitstream.  I am not using the GUI and I have no intentions of dragging or dropping things.  I have already instantied my HLS-generated RTL within a top-level design and would now like to build it.  I use project mode in Vivado and run the whole tihng with Tcl scripts.

 

Has anyone done anything like this?  I have been going through UG902 for guidance, but I find it fairly lacking on tihs subject.  The closest I can get is to export in the IP-XACT format and then load that into the IP Catalog.  I do, in fact, get a VIVADO HLS IP category with my core in it.  My hope would be that I could generate this core and then run "add_files {my_core.xci}", however when I try to generate the core I get:

ERROR: [Common 17-53] User Exception: Remote location is only supported for native IP

 

Any advice is appreciated.

 

Todd

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Observer h4cks4w
Observer
10,785 Views
Registered: ‎08-16-2013

Re: Getting from HLS RTL to implementation through a Tcl script

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Yeah, that was my first post.  I tried to export in the IP-XACT format and pull it in through the IP Catalog.  But as I mentioned there, generating the core did not seem possible.

 

I have found one solution which seems to work.  If you export to System Generator for DSP (Vivado) you get this file:

solutionx/impl/sysgen/my_kernel.xml

 

Within this file, you can find either vivado_hls_impl_verilog_fileset or vivado_hls_impl_vhdl_fileset which are a collection files.  The files are TCLSource, datSource or verilogSource / vhdlSource (at least, that's all I have in my xml file).  You can use the Tcl commands source, "set_property include_dirs" and add_files respectively to pull all of this into your project (or do the analogue if you are using a non-project flow).

 

This at least gets me through synthesis now.

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Teacher muzaffer
Teacher
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Registered: ‎03-31-2012

Re: Getting from HLS RTL to implementation through a Tcl script

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what's wrong with just adding the files from solutionx\syn\verilog?
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Observer h4cks4w
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Registered: ‎08-16-2013

Re: Getting from HLS RTL to implementation through a Tcl script

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Sorry, I skipped a few steps in the process.  That's exactly what I would like to do.  However, I'm doing floating point arithmetic, so I get this in my solutionx/syn/verilog directory:

 

[verilog]$ tree ips
ips
|-- dadd_v7.vhd
|-- daddsub_v7.vhd
|-- dcmp_v7.vhd
|-- ddiv_v7.vhd
|-- dexp_v7.vhd
|-- dlog_v7.vhd
|-- dmul_v7.vhd
|-- dptoi_v7.vhd
|-- drecip_v7.vhd
|-- dsub_v7.vhd
|-- glbl.v
|-- itodp_v7.vhd
`-- libs
    |-- axi_slave_2to1.vhd
    |-- axi_slave_3to1.vhd
    |-- axi_slave_4to1.vhd
    |-- axi_utils_comps.vhd
    |-- axi_utils_v2_0_pkg.vhd
    |-- floating_point_v7_0.vhd
    |-- floating_point_v7_0_comp.vhd
    |-- floating_point_v7_0_consts.vhd
    |-- floating_point_v7_0_exp_table_pkg.vhd
    |-- floating_point_v7_0_pkg.vhd
    |-- floating_point_v7_0_table_pkg.vhd
    |-- floating_point_v7_0_xst.vhd
    |-- floating_point_v7_0_xst_comp.vhd
    |-- glb_ifx_master.vhd
    |-- glb_ifx_slave.vhd
    |-- glb_srl_fifo.vhd
    |-- global_util_pkg.vhd
    |-- mult_gen_v12_0.vhd
    |-- mult_gen_v12_0_comp.vhd
    |-- mult_gen_v12_0_pkg.vhd
    |-- mult_gen_v12_0_xst.vhd
    |-- mult_gen_v12_0_xst_comp.vhd
    |-- xbip_utils_v3_0_pkg.vhd
    `-- xcc_utils_v3_0.vhd

First, I just tried compiling all of those files too, but the floating point files need to be in a floating_point_v7_0 library (I discovered this by looking at the output in the cosim directory).  So, I modified my Tcl script accordingly.  Then when I tried to synthesize I got this:

 

ERROR: [Synth 8-502] non-constant real-valued expression is not supported [/some/path/solution1/syn/verilog/ips/libs/floating_point_v7_0_pkg.vhd:3178]

Then I took a wild guess and tried not giving Vivado the floating_point_v7_0 files in the hope that it was a built-in library that it already had.  This did not turn out to be true:

 

ERROR: [Opt 31-30] Blackbox some/hierarchy/my_kernel_dadd_64ns_64ns_64_4_full_dsp_U10/dadd_v7_u/U0 (floating_point_v7_0) is driving pin D of primitive cell some/hierarchy/my_kernel_dadd_64ns_64ns_64_4_full_dsp_U10/out_buf0_reg[0]. This blackbox cannot be found in the existing library.

At this point I consulted UG902 hoping that there was some way that HLS could package everything up so that it would "just work" with Vivado.  So far, I have not found such a solution.

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Teacher muzaffer
Teacher
7,029 Views
Registered: ‎03-31-2012

Re: Getting from HLS RTL to implementation through a Tcl script

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Apparently another step is necessary to be able to synthesize the output of HLS. Try "Export RTL" on your solution (right click on your solution and use the menu).

Also watch this: http://bcove.me/kbzxo6nu

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Observer h4cks4w
Observer
10,786 Views
Registered: ‎08-16-2013

Re: Getting from HLS RTL to implementation through a Tcl script

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Yeah, that was my first post.  I tried to export in the IP-XACT format and pull it in through the IP Catalog.  But as I mentioned there, generating the core did not seem possible.

 

I have found one solution which seems to work.  If you export to System Generator for DSP (Vivado) you get this file:

solutionx/impl/sysgen/my_kernel.xml

 

Within this file, you can find either vivado_hls_impl_verilog_fileset or vivado_hls_impl_vhdl_fileset which are a collection files.  The files are TCLSource, datSource or verilogSource / vhdlSource (at least, that's all I have in my xml file).  You can use the Tcl commands source, "set_property include_dirs" and add_files respectively to pull all of this into your project (or do the analogue if you are using a non-project flow).

 

This at least gets me through synthesis now.

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