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Explorer
Explorer
1,863 Views
Registered: ‎03-26-2010

HLS 2018.2 csim is BROKEN for CentOS 7.5

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Hi all,

I'm having C simulation (csim_design) issues with absolutely everything on CentOS 7. To make sure it's Xilinx and not my code that's having the problem, I ran C Simulation on the included HLS example code, which could not simulate. Claims there are compilation errors but doesn't give any detail. Vivado 2017.2 works for the same example.

 

Contents of my example_csim.log:

INFO: [SIM 2] *************** CSIM start ***************
INFO: [SIM 4] CSIM will launch GCC as the compiler.
ERR: [SIM 100] 'csim_design' failed: compilation error(s).
INFO: [SIM 3] *************** CSIM finish ***************

 

My console:

Starting C simulation ...
/opt/Xilinx/Vivado/2018.2/bin/vivado_hls /home/XXX/Work/Sandbox/AXI-Lite_Example/axi_lite/proj_axi_lite/solution1/csim.tcl
INFO: [HLS 200-10] Running '/opt/Xilinx/Vivado/2018.2/bin/unwrapped/lnx64.o/vivado_hls'
INFO: [HLS 200-10] For user 'XXX' on host 'YYY' (Linux_x86_64 version 3.10.0-862.11.6.el7.x86_64) on Thu Nov 29 18:09:43 EST 2018
INFO: [HLS 200-10] On os "CentOS Linux release 7.5.1804 (Core) "
INFO: [HLS 200-10] In directory '/home/XXX/Work/Sandbox/AXI-Lite_Example/axi_lite'
INFO: [HLS 200-10] Opening project '/home/XXX/Work/Sandbox/AXI-Lite_Example/axi_lite/proj_axi_lite'.
INFO: [HLS 200-10] Opening solution '/home/XXX/Work/Sandbox/AXI-Lite_Example/axi_lite/proj_axi_lite/solution1'.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 13.3333ns.
INFO: [HLS 200-10] Setting target device to 'xc7z020clg484-2'
INFO: [SIM 211-2] *************** CSIM start ***************
INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s).
INFO: [SIM 211-3] *************** CSIM finish ***************
4
    while executing
"source /home/XXX/Work/Sandbox/AXI-Lite_Example/axi_lite/proj_axi_lite/solution1/csim.tcl"
    invoked from within
"hls::main /home/XXX/Work/Sandbox/AXI-Lite_Example/axi_lite/proj_axi_lite/solution1/csim.tcl"
    ("uplevel" body line 1)
    invoked from within
"uplevel 1 hls::main {*}$args"
    (procedure "hls_proc" line 5)
    invoked from within
"hls_proc $argv"
Finished C simulation.

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Xilinx Employee
Xilinx Employee
1,688 Views
Registered: ‎09-05-2018

Hey @dima2882,

This might but a day late and a dollar short, but - 2018.3 was released yesterday and supports CentOS 7.5.

If you've already changed CentOS 7.4 and don't really care anymore that's fine, but if you're still interested in using CentOS 7.5, I'd be interested to know if your problem is fixed with the new release.

Nicholas Moellers

Xilinx Worldwide Technical Support

View solution in original post

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Xilinx Employee
Xilinx Employee
1,853 Views
Registered: ‎09-05-2018

Hey @dima2882,

Here's the list of supported Linux operating systems from UG973 version 2018.3:

Red Hat Enterprise Workstation/Server 7.2, 7.3, and 7.4 (64-bit)
Red Hat Enterprise Workstation 6.6, 6.7, 6.8, and 6.9 (64-bit)
SUSE Linux Enterprise 11.4 and 12.3 (64-bit)
CentOS 7.2, 7.3, and 7.4 (64-bit)
CentOS 6.7, 6.8, and 6.9 (64-bit)
Ubuntu Linux 16.04.3 LTS (64-bit) 

You'll see that CentOS 7.5 is not listed. Please use a supported operating system.

Nicholas Moellers

Xilinx Worldwide Technical Support
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Explorer
Explorer
1,851 Views
Registered: ‎03-26-2010

Updated the subject of the post to reflect the current state of events.

 

First time I've ever had CentOS to be too NEW on anything... I'll give this a shot on a 7.4 machine.

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Explorer
Explorer
1,801 Views
Registered: ‎03-26-2010

@nmoeller

 

Tried the same design in Vivado 2017.2 - HLS simulates properly.

 

This is really worrisome. I understand Xilinx can't cover every OS for everything and needs to standardize. But, if a minor rev of the OS utterly breaks the newest released version of the tools, and the tools can't even report an error exists, there are issues with the error handling. This is bad...

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Xilinx Employee
Xilinx Employee
1,756 Views
Registered: ‎09-05-2018

Hey @dima2882,

Yes, I agree that it's not ideal, but unfortunately, this is the way the tool is at the moment. That's why it's so important to check with the documentation for each release. I can tell you that from the support side, we have seen a decent amount of these issues, and I would imagine that if we continue to see them, the tool will be enhanced as you suggest.

Nicholas Moellers

Xilinx Worldwide Technical Support
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Xilinx Employee
Xilinx Employee
1,689 Views
Registered: ‎09-05-2018

Hey @dima2882,

This might but a day late and a dollar short, but - 2018.3 was released yesterday and supports CentOS 7.5.

If you've already changed CentOS 7.4 and don't really care anymore that's fine, but if you're still interested in using CentOS 7.5, I'd be interested to know if your problem is fixed with the new release.

Nicholas Moellers

Xilinx Worldwide Technical Support

View solution in original post

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Explorer
Explorer
1,661 Views
Registered: ‎03-26-2010

I can confirm that things simulate for Vivado/HLS 2018.3 and CentOS 7.5.

 

The hilarious thing is that I didn't change the OS - I did my simulation in HLS 2017.2 (which works great in CentOS 7.5), and my compile/generate in 2018.2.

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Visitor
Visitor
1,265 Views
Registered: ‎08-21-2018

Not sure this is the right place to note it, but it's currently broken on Ubuntu 18.04 LTS, which is officially supported.

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Explorer
Explorer
1,262 Views
Registered: ‎03-26-2010

Definitely make a new topic about this, and put in a subject that says this is wrong strongly. Kinda how mine did.

This got a response from key Xilinx person almost immediatly. No one likes seeing their product badmouthed when it's a legitimate problem.

Of course get your ducks in a row and make sure it's really a problem - give 2018.3 a shot, install a 2017.x version, make sure it's not on your end.

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Xilinx Employee
Xilinx Employee
1,243 Views
Registered: ‎09-05-2018

@dima2882 cc@noblis 

Thanks for posting a new thread about this issue; it does make it easier for us to keep track of things, especially since this forum post has already been marked answered.

I'd like to clarify that I posted on this thread quickly only because I knew the answer off hand (i.e., not supported OS), and also, I am far from being a key person here at Xilinx :).

Nicholas Moellers

Xilinx Worldwide Technical Support
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Explorer
Explorer
1,238 Views
Registered: ‎03-26-2010

@nmoeller:

Nicholas - if anyone technical at Xilinx responds to a forum question that person is key :)

I'm sure I speak for everyone on the forum when I say that we all very much appreciate your help!

 

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