I´m working integrating Verilog blackboxes in HLS 2019. 2 thanks to the previous answer in previous thread (https://forums.xilinx.com/t5/High-Level-Synthesis-HLS/HLS-2019-1-Using-blackbox-example-Jason-file/td-p/1031445)
Mi question is if it is possible to add XDC restriction in the Jason file. We have a multicylcle path in the “blackboxed” RTL and it would be interesting to embed the XDC code.
Another question if the VHDL blackbox is in the roadmap. We have still a lot of VHDL code…
Best Regards, GS