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sfalcke
Visitor
Visitor
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Registered: ‎10-02-2018

HLS 2020.2: ap_memory interface ignores latency setting

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Hello,

the following code inserts a 3 clock latency on the ap_memory interfaces when compiled with HLS 2019.1, but none using HLS 2020.2, ignoring "latency=3":

void HlsRegisterFile(uint64 * AxiStream, ap_uint<3> Operation, uint32 RoMemOffset, uint32 RwMemOffset,
		             ap_uint<10> RoCount64, ap_uint<10> RwCount64,
					 uint64 RO_RegInputs[1024], uint64 RW_RegOutputs[1024])
{

#ifdef __VITIS_HLS__
	// vitis HLS 2020.2:
	#pragma HLS INTERFACE ap_memory port=RW_RegOutputs storage_type=ram_1p latency=3
	#pragma HLS INTERFACE ap_memory port=RO_RegInputs storage_type=ram_1p latency=3
#else
	// vivado HLS 2019.1:
	#pragma HLS INTERFACE ap_memory port=RW_RegOutputs
	#pragma HLS INTERFACE ap_memory port=RO_RegInputs
	#pragma HLS RESOURCE variable=RW_RegOutputs core=RAM_1P latency=3
	#pragma HLS RESOURCE variable=RO_RegInputs core=RAM_1P latency=3
#endif

	#pragma HLS INTERFACE s_axilite port=RoMemOffset bundle=CNTRL
	#pragma HLS INTERFACE s_axilite port=RwMemOffset bundle=CNTRL
	#pragma HLS INTERFACE m_axi depth=512 port=AxiStream offset=off

    for (int op = 0; op < 3; op++)
    {
		switch (op)
		{
			case 0:
				if (Operation & 0x01)
				{
					// byte offset -> 64 bit word offset
					uint64 * stream = AxiStream + (RwMemOffset >> 3);

					// get r/w register data from AXI master interface:
					for (int i = 0; i < RwCount64; i++)
					{
						RW_RegOutputs[i] = * stream++;
					}
				}
				break;

			case 1:
...
		}
    }
}

 I have learned that "latency" has been moved from #pragma RESOURCE to #pragma INTERFACE in HLS 2020.2, therefore the two sets of #pragmas above.

Any suggestions?

 

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sfalcke
Visitor
Visitor
362 Views
Registered: ‎10-02-2018

Hi Randy,

to wrap up the issue, here is the solution as we discussed in our private conversation:

The pragmas as used in the initial code example are correct.
The different behavior of the HLS 2019.1 and 2020.2 versions is due to the different default setting of the pipeline_loops parameter.
This is 0 in 2019.1 and 64 in 2020.2.
Therefore, version 2020.2 generates burst accesses to the external memory. There are two ways to prevent this:
a.) Change the pipeline_loops parameter globally: set solution -> solution settings -> config_compile -> pipeline_loops = 0
b.) Disable pipelining individually in each affected memory access loop by inserting #pragma HLS PIPELINE off

for (int i = 0; i < RwCount64; i++)
{
    #pragma HLS PIPELINE off
    RW_RegOutputs[i] = * stream++;
}

With one of these changes applied, HLS 2020.2 also generates wait states between memory accesses.

Thanks for the support,
Stefan

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randyh
Xilinx Employee
Xilinx Employee
757 Views
Registered: ‎01-04-2013

I believe BIND_STORAGE is the replacement for RESOURCE. I don't know why the INTERFACE latency is not working, but can you try it with BIND_STORAGE instead? 

	#pragma HLS INTERFACE ap_memory port=RW_RegOutputs
	#pragma HLS INTERFACE ap_memory port=RO_RegInputs
	#pragma HLS BIND_STORAGE variable=RW_RegOutputs type=RAM_1P latency=3
	#pragma HLS BIND_STORAGE variable=RO_RegInputs type=RAM_1P latency=3

 

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sfalcke
Visitor
Visitor
748 Views
Registered: ‎10-02-2018

Thank you for your help!

Unfortunately, with this pragmas I get:

WARNING: [HLS 214-185] The resource pragma (storage) on function argument, in 'call' is unsupported 

So, BIND_STORAGE seems to work for variables only.

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randyh
Xilinx Employee
Xilinx Employee
642 Views
Registered: ‎01-04-2013

Hi,

 

Sorry about the delayed response. I will file a CR to see about fixing the issue. Is there any chance you could share your design for a test case? 

Thanks,
Randy

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sfalcke
Visitor
Visitor
597 Views
Registered: ‎10-02-2018

Hi Randy,

here are two almost identical projects, one is set up for HLS 2019.1, the other for HLS 2020.2.

Both compile and simulate just fine, but the 2020.2 version lacks the memory wait states.

Best regards,

Stefan

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sfalcke
Visitor
Visitor
363 Views
Registered: ‎10-02-2018

Hi Randy,

to wrap up the issue, here is the solution as we discussed in our private conversation:

The pragmas as used in the initial code example are correct.
The different behavior of the HLS 2019.1 and 2020.2 versions is due to the different default setting of the pipeline_loops parameter.
This is 0 in 2019.1 and 64 in 2020.2.
Therefore, version 2020.2 generates burst accesses to the external memory. There are two ways to prevent this:
a.) Change the pipeline_loops parameter globally: set solution -> solution settings -> config_compile -> pipeline_loops = 0
b.) Disable pipelining individually in each affected memory access loop by inserting #pragma HLS PIPELINE off

for (int i = 0; i < RwCount64; i++)
{
    #pragma HLS PIPELINE off
    RW_RegOutputs[i] = * stream++;
}

With one of these changes applied, HLS 2020.2 also generates wait states between memory accesses.

Thanks for the support,
Stefan

View solution in original post

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