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3,921 Views
Registered: ‎02-15-2014

HLS AXI Master missing word

Hello,

I'm implementing a AXI Master DMA in HLS to transfer a burst of data from PL to DDR3. I limited the zynq memory to 512 Mbyte (on microzed) and I want to use the address from 0x3000 0000 as shared memory between PL and PS.

The transaction (32*256 kword int32)  is triggered by an external interrupt every ms (interrupt_data). Every 1000 transaction (one per second) a interrupt for the processor is fired. The driver on the processor copy the 1000 buffers to the user space.

 

#define N 32*256

#include <stdio.h>
#include <string.h>
#include "example.hpp"

void example(volatile int *a, int stream_in[N], unsigned int byte_wroffset,
unsigned int ctrl_reg, unsigned int *status_reg, unsigned int *ip_version, bool *interrupt_r, bool interrupt_data )

At the moment, just for test, I replaced the access to the input data bus (bram) with a costant 0 and for simplicity I'm always write from address 0x3000 0000 to 0x3000 0000 + 32*256. 
{
#pragma HLS INTERFACE m_axi port=a

#pragma HLS INTERFACE bram port=stream_in
#pragma HLS INTERFACE s_axilite port=byte_wroffset bundle=BUS_AL
#pragma HLS INTERFACE s_axilite port=ctrl_reg bundle=BUS_AL
#pragma HLS INTERFACE s_axilite port=status_reg bundle=BUS_AL
#pragma HLS INTERFACE s_axilite port=ip_version bundle=BUS_AL
#pragma HLS INTERFACE ap_ovld port=interrupt_r


int i;
static unsigned int count=0;
static unsigned int packet=0;
static unsigned int offset=0;
static unsigned int pingpong=0;
static bool int_pending = false;
static unsigned int local_ctrl_reg=0;

*ip_version=IP_VERSION;
local_ctrl_reg = ctrl_reg;
if ((local_ctrl_reg & START_MASK) && (interrupt_data==true)){ //&& (int_pending == false)
for(i=0; i < N; i++)
{
#pragma HLS PIPELINE II=1
a[i+byte_wroffset/4] = 0;
}
offset+=N;
count += N;
*status_reg = count;

if (packet==999)
{
int_pending = true;
packet=0;
pingpong++;
if (pingpong==2)
{
pingpong=0;
offset=0;
}
}
else
{
packet++;
}

}
if (local_ctrl_reg & CLEARINT_MASK) {
int_pending=false;
}
*interrupt_r=int_pending;
}

 

 

When i try to read on the Zynq the data from adress 0x3000 0000 i get

 

 

[ 180.263779] [NI] val( 0):=0xBAC51717
[ 180.267799] [NI] val( 1):=0x9C57BB7C
[ 180.271875] [NI] val( 2):=0x00000000
[ 180.275954] [NI] val( 3):=0x00000000
[ 180.280034] [NI] val( 4):=0x00000000
[ 180.284113] [NI] val( 5):=0x00000000
[ 180.288193] [NI] val( 6):=0x00000000
[ 180.292272] [NI] val( 7):=0x00000000
[ 180.296352] [NI] val( 8):=0x00000000
[ 180.300432] [NI] val( 9):=0x00000000
[ 180.304511] [NI] val( 10):=0x00000000
[ 180.308591] [NI] val( 11):=0x00000000
[ 180.312671] [NI] val( 12):=0x00000000
[ 180.316750] [NI] val( 13):=0x00000000
[ 180.320830] [NI] val( 14):=0x00000000
[ 180.324909] [NI] val( 15):=0x00000000
[ 180.328989] [NI] val( 16):=0x00000000
[ 180.333068] [NI] val( 17):=0x00000000
[ 180.337148] [NI] val( 18):=0x00000000
[ 180.341228] [NI] val( 19):=0x00000000
[ 180.345307] [NI] val( 20):=0x00000000
[ 180.349387] [NI] val( 21):=0x00000000
[ 180.353466] [NI] val( 22):=0x00000000
[ 180.357546] [NI] val( 23):=0x00000000
[ 180.361626] [NI] val( 24):=0x00000000
[ 180.365705] [NI] val( 25):=0x00000000
[ 180.369785] [NI] val( 26):=0x00000000
[ 180.373865] [NI] val( 27):=0x00000000
[ 180.377944] [NI] val( 28):=0x00000000
[ 180.382024] [NI] val( 29):=0x00000000
[ 180.386103] [NI] val( 30):=0xFB37BE77
[ 180.390183] [NI] val( 31):=0x24FF819B
[ 180.394263] [NI] val( 32):=0x6EDE2F96
[ 180.398342] [NI] val( 33):=0x376FCDFF
[ 180.402422] [NI] val( 34):=0x00000000
[ 180.406501] [NI] val( 35):=0x00000000
[ 180.410581] [NI] val( 36):=0x00000000
[ 180.414660] [NI] val( 37):=0x00000000
[ 180.418740] [NI] val( 38):=0x00000000
[ 180.422820] [NI] val( 39):=0x00000000
[ 180.426899] [NI] val( 40):=0x00000000
[ 180.430979] [NI] val( 41):=0x00000000
[ 180.435059] [NI] val( 42):=0x00000000
[ 180.439138] [NI] val( 43):=0x00000000
[ 180.443218] [NI] val( 44):=0x00000000
[ 180.447298] [NI] val( 45):=0x00000000
[ 180.451377] [NI] val( 46):=0x00000000
[ 180.455456] [NI] val( 47):=0x00000000
[ 180.459536] [NI] val( 48):=0x00000000
[ 180.463616] [NI] val( 49):=0x00000000
[ 180.467695] [NI] val( 50):=0x00000000
[ 180.471775] [NI] val( 51):=0x00000000
[ 180.475854] [NI] val( 52):=0x00000000
[ 180.479934] [NI] val( 53):=0x00000000
[ 180.484014] [NI] val( 54):=0x00000000
[ 180.488093] [NI] val( 55):=0x00000000
[ 180.492173] [NI] val( 56):=0x00000000
[ 180.496253] [NI] val( 57):=0x00000000
[ 180.500332] [NI] val( 58):=0x00000000
[ 180.504412] [NI] val( 59):=0x00000000
[ 180.508491] [NI] val( 60):=0x00000000
[ 180.512571] [NI] val( 61):=0x00000000
[ 180.516651] [NI] val( 62):=0x6E43DF74
[ 180.520730] [NI] val( 63):=0x3613F3BE
[ 180.524810] [NI] val( 64):=0x35F9FCAE
[ 180.528889] [NI] val( 65):=0xDDEE2FB1
[ 180.532969] [NI] val( 66):=0x00000000
[ 180.537048] [NI] val( 67):=0x00000000
[ 180.541128] [NI] val( 68):=0x00000000
[ 180.545208] [NI] val( 69):=0x00000000
[ 180.549287] [NI] val( 70):=0x00000000
[ 180.553367] [NI] val( 71):=0x00000000
[ 180.557446] [NI] val( 72):=0x00000000
[ 180.561526] [NI] val( 73):=0x00000000
[ 180.565606] [NI] val( 74):=0x00000000
[ 180.569685] [NI] val( 75):=0x00000000
[ 180.573765] [NI] val( 76):=0x00000000
[ 180.577845] [NI] val( 77):=0x00000000
[ 180.581924] [NI] val( 78):=0x00000000
[ 180.586004] [NI] val( 79):=0x00000000
[ 180.590083] [NI] val( 80):=0x00000000
[ 180.594163] [NI] val( 81):=0x00000000
[ 180.598242] [NI] val( 82):=0x00000000
[ 180.602322] [NI] val( 83):=0x00000000
[ 180.606402] [NI] val( 84):=0x00000000
[ 180.610481] [NI] val( 85):=0x00000000
[ 180.614561] [NI] val( 86):=0x00000000
[ 180.618640] [NI] val( 87):=0x00000000
[ 180.622720] [NI] val( 88):=0x00000000
[ 180.626800] [NI] val( 89):=0x00000000
[ 180.630879] [NI] val( 90):=0x00000000
[ 180.634959] [NI] val( 91):=0x00000000
[ 180.639038] [NI] val( 92):=0x00000000
[ 180.643118] [NI] val( 93):=0x00000000
[ 180.647198] [NI] val( 94):=0x00000101
[ 180.651277] [NI] val( 95):=0x2653DA00
[ 180.655357] [NI] val( 96):=0x00000001
[ 180.659437] [NI] val( 97):=0x947F54AE
[ 180.663516] [NI] val( 98):=0x00000000
[ 180.667596] [NI] val( 99):=0x00000000
[ 180.671675] [NI] val( 100):=0x00000000
[ 180.675755] [NI] val( 101):=0x00000000
[ 180.679835] [NI] val( 102):=0x00000000
[ 180.683914] [NI] val( 103):=0x00000000
[ 180.687994] [NI] val( 104):=0x00000000
[ 180.692073] [NI] val( 105):=0x00000000
[ 180.696153] [NI] val( 106):=0x00000000
[ 180.700233] [NI] val( 107):=0x00000000
[ 180.704312] [NI] val( 108):=0x00000000
[ 180.708392] [NI] val( 109):=0x00000000
[ 180.712471] [NI] val( 110):=0x00000000
[ 180.716551] [NI] val( 111):=0x00000000
[ 180.720631] [NI] val( 112):=0x00000000
[ 180.724710] [NI] val( 113):=0x00000000
[ 180.728790] [NI] val( 114):=0x00000000
[ 180.732869] [NI] val( 115):=0x00000000
[ 180.736949] [NI] val( 116):=0x00000000
[ 180.741028] [NI] val( 117):=0x00000000
[ 180.745108] [NI] val( 118):=0x00000000
[ 180.749188] [NI] val( 119):=0x00000000
[ 180.753267] [NI] val( 120):=0x00000000
[ 180.757347] [NI] val( 121):=0x00000000
[ 180.761426] [NI] val( 122):=0x00000000
[ 180.765506] [NI] val( 123):=0x00000000
[ 180.769586] [NI] val( 124):=0x00000000
[ 180.773665] [NI] val( 125):=0x00000000
[ 180.777745] [NI] val( 126):=0x28DEFF8F
[ 180.781825] [NI] val( 127):=0xADDDE37E

 

As you can see, every 30 word i have 4 word not written.

I'm sure that the HLS core is skipping that because i tested in linux to write one of that with rwmem command. If I readback that cell (even after a reboot) the value written by linux is unchanged.

If I start a write cycle by the HLS core the value remain unchanged.

The axi bus (slave) on zynq is configured as 64 bit wide. If I try to configure as 32 bit nothing works...

 

I tried almost everything and i can't find a solution.

 

Thanks

Andrea

 

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2 Replies
Highlighted
Moderator
Moderator
3,886 Views
Registered: ‎04-17-2011

Re: HLS AXI Master missing word

Moving to HLS board.
Regards,
Debraj
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Highlighted
411 Views
Registered: ‎08-05-2019

Re: HLS AXI Master missing word

Hello,

I'm suffering the same thing like yours, have you solved the problem?

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