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nanson
Explorer
Explorer
869 Views
Registered: ‎08-31-2017

HLS ERROR: [BIND 205-201] Array is allocated with multiple cores: RAM_1P, RAM_2P.

Hi,

I designed the following code in function template. However, it fired the following issues while adding "#pragma HLS RESOURCE variable=O_VEC core=RAM_2P".

After removing the pragma, the HLS compile is PASS. However, for the function argument O_VEC, it can be initialized from the AXI lite interface and also updated the value by the internal operation inside. That's why I would like to use RAM_2P. Is there anything worng ?  Does anyone know what HLS complains ?  Thanks

 

INFO: [BIND 205-101] Exploring resource sharing.
ERROR: [BIND 205-201] Array 'O_VEC' is allocated with multiple cores: RAM_1P, RAM_2P.
ERROR: [BIND 205-201] Array 'O_VEC' is allocated with multiple cores: RAM_1P, RAM_2P.
INFO: [BIND 205-100] Finished micro-architecture generation.

const unsigned int W_SIZE = 2;

typedef float data_t;
 
template<int SIZE, class T>
void mi_cpg(T wd0, \
T wd1, \
T mi, \
T O_VEC[SIZE]
)
{

T A_VEC[SIZE];
T W_MAT[SIZE][SIZE];

W_MAT[0][0]= wd0;
W_MAT[0][1]= wd1+mi;
W_MAT[1][0]= -(wd1+mi);
W_MAT[1][1]= wd0;
 
T temp_sum = 0;
T O_vec_tmp;

OUTER_CPG_MVM: for (int i = 0;i < SIZE; i++) {
INNER_CPG_MVM: for (int j = 0; j < SIZE; j++) {
O_vec_tmp = O_VEC[j];
temp_sum = temp_sum + W_MAT[i][j] * O_vec_tmp;
}
A_VEC[i] = temp_sum;
temp_sum = 0;
}


T A_VEC_TANH_tmp;
 
CPG_OUT_TANH: for(int i=0; i < SIZE; ++i) {
A_VEC_TANH_tmp = A_VEC[i];
O_VEC[i] = A_VEC_TANH_tmp+1;
}


}


void mi_cpg_top(data_t wd0, \
data_t wd1, \
data_t mi, \
data_t O_VEC[2]
)
{
#pragma HLS INTERFACE s_axilite port=return bundle=CTRL_BUS
#pragma HLS INTERFACE s_axilite port=wd0 bundle=CTRL_BUS
#pragma HLS INTERFACE s_axilite port=wd1 bundle=CTRL_BUS
#pragma HLS INTERFACE s_axilite port=mi bundle=CTRL_BUS
#pragma HLS INTERFACE s_axilite port=O_VEC bundle=CTRL_BUS

#pragma HLS RESOURCE variable=O_VEC core=RAM_2P

mi_cpg<2,data_t>(wd0,wd1,mi,O_VEC);

}
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4 Replies
nmoeller
Xilinx Employee
Xilinx Employee
853 Views
Registered: ‎09-05-2018

Hey @nanson ,

An AXI4-Lite interface can only handle one port, so the RAM_1P is implied. If you look at the AXI4-Lite Spec, in the case of a simulataneous read and write, the read is handled first. If you need a dual port ram for your design, you will need to use a different interface.

Nicholas Moellers

Xilinx Worldwide Technical Support
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nanson
Explorer
Explorer
847 Views
Registered: ‎08-31-2017

 

What I thought was to initialize the array via AXI slave lite in the beginning. After initialization and then start, the internal operation will read from the array and update the value to the array accordingly. Thus, it needs one port from AXI lite and one port from internal logic.

If that's the case, what's your suggestion to achieve it in HLS?

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nmoeller
Xilinx Employee
Xilinx Employee
840 Views
Registered: ‎09-05-2018

@nanson,

If you need one port for internal logic and one for axi4 lite, you might split up the signal into two separate arrays, one for reads and one for writes. But I don't really know what is meant by "one port for internal logic". Also, since the array length is just 2, it's a good candidate to be split up into registers.

Nicholas Moellers

Xilinx Worldwide Technical Support
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nanson
Explorer
Explorer
838 Views
Registered: ‎08-31-2017

@nmoeller 

Thanks for the comment.

In the beginning, the initial value of O_VEC will be cofigured from the AXI lite from CPU. Then, CPU will enable the module to generate output. The module will calculate the output value according to the configuration parameters and initial configured value. The internal logic means the arithmetic operation inside the HLS module. That the "one port for internal logic" I mentioned in the previous post which the initial vale of O_VEC comes from CPU and HLS will use it for new values afterwards.

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