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Observer immi4net
Observer
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Registered: ‎06-24-2011

HLS FSM, signal input change not registering

Hi, 

I have written an FSM using case statements and in one state, need to check the input for the transition but it seems input is not registered and remains in blocking condition.

code snippet

 

#pragma HLS INTERFACE s_axilite port=mode bundle=Regs
case 1:
statement1;
statement2;
state++;
break;
case 2:
statement1;
statement2;

while (mode == 0){
ap_wait()
}
sate++;
break;
case 3:
statement1;
statement2;
break;


 

in the above code case 0, 1  are running fine in case 2 i have blocked the state until mode changes.

I have changed the mode from SW but it doesn't register here and the while loop remains blocked.

after a lot of HW debugging it seems that the HLS IP takes the axi registers values only in the start phase and used the same value until goes to IDLE and only changes when starts again.

How can i make the mode register to be latched concurrently while in the case statement?    

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