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shagarwal
Visitor
Visitor
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Registered: ‎09-26-2020

HLS Report not showing details of loops inside sub module/function

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Hi,

I implemented a design where the top level function (conv_layer) is calling 2 other sub functions (compute_engine1 & compute_engine2). Each sub function has 2 loops each.

But after the C synthesis, the report only mentions the latency/throughput for the sub modules as a whole. I am not able to see the latencies associated with loops inside them. Can we only see reports for loops inside top level function ?

Is there any way to overcome this issue ? (Images attached)

 

Thanks

shagarwal

CODE:

void compute_engine1(fx IN[227][227][3], fx OUT[55][55][96], fx *MEM){
	fx W1[3][96];
	#pragma HLS ARRAY_PARTITION variable=W1 complete dim=1

	for(int r = 0; r < 55; ++r){									//3025
	 	compute_engine1_label0:for(int c = 0; c < 55; ++c){
			#pragma HLS PIPELINE
	 		for(int y = 0; y < 96; ++y){
	 			#pragma HLS UNROLL
				OUT[r][c][y] = 0;
	 		}
	 	}
	 }

	//Computation
	for(int i = 0; i < 11; ++i){									//3e7
		for(int j = 0; j < 11; ++j){
				memcpy(W1, MEM + (i*11*3*96 + j*3*96), 3*96*sizeof(fx));
			for(int r = 0; r < 55; r += 1){
				for(int c = 0; c < 55; c += 1){
					for(int y = 0; y < 96; ++y){
						#pragma HLS PIPELINE
						for(int x = 0; x < 3; ++x){
							#pragma HLS UNROLL
							OUT[r][c][y] += IN[r+i][c+j][x] * W1[x][y];
						}
					}
				}
			}
		}
	}
}

void compute_engine2(fx IN[55][55][96], fx OUT[27][27][96]){
	
	for(int r = 0; r < 27; ++r){
	 	for(int c = 0; c < 27; ++c){
		#pragma HLS PIPELINE
	 		for(int y = 0; y < 96; ++y){
	 			#pragma HLS UNROLL
				OUT[r][c][y] = 0;
	 		}
	 	}
	 }

	//Computation
	for(int i = 0; i < 3; ++i){
		for(int j = 0; j < 3; ++j){
			for(int r = 0; r < 27; r += 2){
				for(int c = 0; c < 27; c += 2){
					for(int y = 0; y < 96; ++y){
						#pragma HLS PIPELINE
						for(int x = 0; x < 96; ++x){
							#pragma HLS UNROLL
							if(IN[r+i][c+j][x] > OUT[r][c][y])
								OUT[r][c][y] = IN[r+i][c+j][x];
						}
					}
				}
			}
		}
	}
}

void conv_layer(fx *MEM){	//TODO: Check if 2 posts can be used ?
	#pragma HLS INTERFACE m_axi depth=1000000000 port=MEM offset=direct bundle=MEM

	//Partitioned along DIN => DIN buffers of size R*C fx sized words each
	fx IN0[227][227][3];
	#pragma HLS ARRAY_PARTITION variable=IN0 complete dim=3

	fx IN1[55][55][96];
	#pragma HLS ARRAY_PARTITION variable=IN1 complete dim=3

	fx IN2[27][27][96];
	#pragma HLS ARRAY_PARTITION variable=IN2 complete dim=3

	 compute_engine1(IN0, IN1, MEM);
	 compute_engine2(IN1, IN2);
}

 REPORT:

No info shown for the loopsNo info shown for the loops

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nithink
Xilinx Employee
Xilinx Employee
503 Views
Registered: ‎09-04-2017

@shagarwal   Did you click on the links for the instances?  grp_compute_engine*

Thanks,

Nithin

View solution in original post

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nithink
Xilinx Employee
Xilinx Employee
504 Views
Registered: ‎09-04-2017

@shagarwal   Did you click on the links for the instances?  grp_compute_engine*

Thanks,

Nithin

View solution in original post

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