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Observer
Observer
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Registered: ‎06-19-2015

HLS cosimulation: multiple AXI-lite writes with multiple calls

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Hello,

I have a simple module with 2 input interfaces (AXI-lite and AXI-stream) and one output (AXI-stream).

I want to do a test similar to my VHDL test:

1. Configure with AXI-lite.
2. Send data via AXI-stream.

I do not want to send the data via AXI-stream until the module has been configured. And in the following calls I don't want it reconfigured.

But when I make multiple calls the AXI-lite bus is rewritten.

Is there any way this does not happen?

 

wave.png


Thank you.

#include <array>

void top(int dataIn,std::array<int,2> &refs,int *dataOut){
  #pragma HLS INTERFACE axis port=dataIn
  #pragma HLS ARRAY_PARTITION variable=refs complete
  #pragma HLS INTERFACE s_axilite port=refs bundle=control offset=0x0000
  #pragma HLS INTERFACE axis port=dataOut

  int tmp;
  int a;
  int b;

  a = refs[0];
  b = refs[1];

  tmp = a + b + dataIn;

  *dataOut = tmp;
}
#include "../src/top.h"

int main(void){
  std::array<int,2> refs;
  int dataIn;
  int dataOut;

  //AXI-lite configuration
  refs[0] = 1;
  refs[1] = 1;
  top(dataIn,refs,&dataOut);
  //AXI-stream 0
  dataIn = 4;
  top(dataIn,refs,&dataOut);
  //AXI-stream 1
  dataIn = 7;
  top(dataIn,refs,&dataOut);

  return 0;
}

 

 

 

 

 

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Xilinx Employee
Xilinx Employee
490 Views
Registered: ‎09-05-2018

Re: HLS cosimulation: multiple AXI-lite writes with multiple calls

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Hey @carruinar,

What you describe sounds like you may be able to use an else statement. You might also need to add a fourth input, some sort of boolean, which controls whether you want to read the axi lite or axi stream variable.

#include <array>

void top(int dataIn,std::array<int,2> &refs,int *dataOut){
  #pragma HLS INTERFACE axis port=dataIn
  #pragma HLS ARRAY_PARTITION variable=refs complete
  #pragma HLS INTERFACE s_axilite port=refs bundle=control offset=0x0000
  #pragma HLS INTERFACE axis port=dataOut

  int tmp;
  static int a = -1;
  static int b = -1;

if( a == -1 ) { a = refs[0]; b = refs[1]; } else {
tmp = a + b + dataIn; *dataOut = tmp;
} }
Nicholas Moellers

Xilinx Worldwide Technical Support

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Xilinx Employee
Xilinx Employee
544 Views
Registered: ‎09-05-2018

Re: HLS cosimulation: multiple AXI-lite writes with multiple calls

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Hey @carruinar ,

If you use the keyword static on a variable, the value is saved through repeated calls to the IP. I would suggest something like that following:

#include <array>

void top(int dataIn,std::array<int,2> &refs,int *dataOut){
  #pragma HLS INTERFACE axis port=dataIn
  #pragma HLS ARRAY_PARTITION variable=refs complete
  #pragma HLS INTERFACE s_axilite port=refs bundle=control offset=0x0000
  #pragma HLS INTERFACE axis port=dataOut

  int tmp;
  static int a = -1;
  static int b = -1;

if( a == -1 ) { a = refs[0]; b = refs[1]; }
tmp = a + b + dataIn; *dataOut = tmp; }

 Of course, you could use a different condition to set a and b, perhaps a new input.

Nicholas Moellers

Xilinx Worldwide Technical Support
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Observer
Observer
505 Views
Registered: ‎06-19-2015

Re: HLS cosimulation: multiple AXI-lite writes with multiple calls

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Thank you for the reply @nmoeller

Yes, I forgot the static type.

Is there a way that when I make a function call, an AXI-Stream or AXI-lite transaction does not start? For example:

top(dataIn,refs,&dataOut); //Only AXI-lite
top(dataIn,refs,&dataOut); //Only AXI-stream
top(dataIn,refs,&dataOut); //Only AXI-stream

 

 

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Highlighted
Xilinx Employee
Xilinx Employee
491 Views
Registered: ‎09-05-2018

Re: HLS cosimulation: multiple AXI-lite writes with multiple calls

Jump to solution

Hey @carruinar,

What you describe sounds like you may be able to use an else statement. You might also need to add a fourth input, some sort of boolean, which controls whether you want to read the axi lite or axi stream variable.

#include <array>

void top(int dataIn,std::array<int,2> &refs,int *dataOut){
  #pragma HLS INTERFACE axis port=dataIn
  #pragma HLS ARRAY_PARTITION variable=refs complete
  #pragma HLS INTERFACE s_axilite port=refs bundle=control offset=0x0000
  #pragma HLS INTERFACE axis port=dataOut

  int tmp;
  static int a = -1;
  static int b = -1;

if( a == -1 ) { a = refs[0]; b = refs[1]; } else {
tmp = a + b + dataIn; *dataOut = tmp;
} }
Nicholas Moellers

Xilinx Worldwide Technical Support

View solution in original post

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