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2,947 Views
Registered: ‎09-11-2017

HLS export whole vhdl code possible?

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Hi There,

I am working on a project where I need a floating point resource which I have developed using HLS project in C++, I exported this as an IP and this works perfectly as expected. This floating point resource is carefully tweeked in HLS for needed specifications. My top level design which is apparently a vhdl(RTL) project need to instantiate this Auto-generated HLS IP. Here is what I tried:

-> I created a Xilinx IP packager project added all my hand-written vhdl codes,

-> Created a block diagram in the same project

-> Added HLS IP, made ports external

-> Created a vhdl wrapper(auto-generated)

-> Instantiated this wrapper in my top-level module as needed

-> Did my Smulations

-> Packed my top-level module as IP

Here is what I observe:

-> Behavioral, post synthesis and post implementation functional and timing simulation succeeded (my IP packager project before and after final packaging)

-> Above said observation is very sensitive to the folder organization and ip repository location which makes my final packaged Ip(top level) highly unstable.

-> my top level packaged IP (which intern has an HLS IP inside it) most of the times shows that HLS auto-generated IP becomes black box

-> Looking more closer to previous observation It magically deletes the complete .src folder!

-> When I Hack this by copying and re-adding .src at required location it works!

 

Furthermore, I am under an impression that I pull my internal wires outside and convert them to top-level ports package my ip which has pure RTL description and later connect the HLS IP and my Top-level IP in a final Block diagram in new project.

 

My question are:

1) Is there a way to hierarchically stably pack my RTL description and HLS IP in a proper directory organization both together which would make a single IP which has another IP inside itself?

2)  Is it possible to openly find the whole auto-generated vhdl code of HLS project?  which would possibly make my whole final packager project pure RTL (I tried to put vhdl code that was visible in HLS auto-generation and most of the component instantiations are missing)

 

Please help me figure out how I can possibly solve this as I have been revolving around this like an Inception for weeks :p

 

Thanks & Regards,

Hemanth

 

 

 

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Voyager
Voyager
3,626 Views
Registered: ‎06-24-2013

Hey @hemanthsingh_in,

 

what does this tcl file do?

could you please go through if this tcl generates something?

The TCL script creates and configures the IP cores used in your HDL.

It also generates the HDL required for synthesis from the XCI file.

 

If you don't want to generate the IP cores (which is the default) you can instead generate the targets for synthesis/simulation/implementation and use that instead, but you will lose some flexibility.

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!

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Voyager
Voyager
2,927 Views
Registered: ‎06-24-2013

Hey @hemanthsingh_in,

 

Is there a way to hierarchically stably pack my RTL description and HLS IP in a proper directory organization both together which would make a single IP which has another IP inside itself?

This should work when you do not copy around stuff manually (i.e. outside the tools).

 

Is it possible to openly find the whole auto-generated vhdl code of HLS project?  which would possibly make my whole final packager project pure RTL

In HLS, the following commands will write out the HDL/RTL code ...

csynth_design
export_design -flow syn -rtl vhdl -format ip_catalog

You will then find a number of VHDL (or Verilog) files in the solution folder (under vhdl or verilog) which contains the HDL sources for your HLS project (and all components).

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!
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2,918 Views
Registered: ‎09-11-2017

Hi @hpoetzl, Thanks for your reply. I just noticed that the command you mentioned is essentially the same command in auto generated tcl script after run rtl synthesis button press
 ############################################################
## This file is generated automatically by Vivado HLS.
## Please DO NOT edit it.
## Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
############################################################
open_project proj_types_float_double
set_top types_float_double
add_files types_float_double.c
add_files -tb types_float_double_test.c
add_files -tb result.golden.dat
open_solution "solution1"
set_part {xc7z010clg400-1}
create_clock -period 30 -name default
#source "./proj_types_float_double/solution1/directives.tcl"
csim_design
csynth_design
cosim_design -rtl vhdl
export_design -rtl vhdl -format ip_catalog -description "Adder floating point single precition pipeline 1 stage" -version "2.0" -display_name "Adder_p1"

And I noticed that its still the same that is there are only 3 files generated 1 of them is again a tcl as can be seen in the snapshot.

Could you please elaborate? Did I get you wrong?

Screen Shot 2017-09-24 at 7.20.16 PM.png
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Voyager
Voyager
2,899 Views
Registered: ‎06-24-2013

Hey @hemanthsingh_in,

 

And I noticed that its still the same that is there are only 3 files generated 1 of them is again a tcl ...

Could you please elaborate? Did I get you wrong?

It really depends on your HLS code, in some cases a single HDL file is all Vivado HLS produces and in other cases it is a huge number of entities forming your HDL IP. It really depends on what your HLS code uses (resource/core wise) and what interfaces/ports are defined.

 

Best,

Herbert

-------------- Yes, I do this for fun!
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2,889 Views
Registered: ‎09-11-2017

Hi @hpoetzl,

 

I have Created a vivado project and imported these files which are auto-generated as you can see in the screenshot there is a component which is missing. I have attached this project which has these two files and the auto-generated tcl what does this tcl file do? could you please go through if this tcl generates something? I am not sure how to use this tcl. I have attached this project.  

Thanks & Regards,
Hemanth

Screen Shot 2017-09-24 at 10.05.13 PM.png
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Voyager
Voyager
3,627 Views
Registered: ‎06-24-2013

Hey @hemanthsingh_in,

 

what does this tcl file do?

could you please go through if this tcl generates something?

The TCL script creates and configures the IP cores used in your HDL.

It also generates the HDL required for synthesis from the XCI file.

 

If you don't want to generate the IP cores (which is the default) you can instead generate the targets for synthesis/simulation/implementation and use that instead, but you will lose some flexibility.

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!

View solution in original post

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2,785 Views
Registered: ‎09-11-2017

Thank you @hpoetzl for your replies and support. So by this post I understand that whole vhdl code export without creating an IP is not possible from HLS and trying this is unstable because this is not what HLS is intended to be used for by default. If this is not correct please pin me to post and your valuable suggestions are welcome and I am closing the post.

 

Thanks & Regards,

Hemanth

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1,995 Views
Registered: ‎07-04-2017

Hi,

@hpoetzl
@hemanthsingh_in
Did any of you get to successfully run the automatically generated .tcl files for ip cores in vivado hls and generate their corresponding verilog code? If yes, would you please share the command you were running to use those .tcl files?

Thanks

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