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11-05-2019 05:24 AM - edited 11-06-2019 09:03 AM
The for-loop in the following code generates an unknow error. Any idea ?
producer0.cpp
#include "producer0.h" #include <stdint.h> #define OFFSET_DDR 0x20000000 using sc_core::sc_module; producer0::producer0(sc_core::sc_module_name name) :sc_module(name) { SC_CTHREAD(thread, clock.pos()); reset_signal_is(reset, true); } void producer0::thread() { unsigned long data[16] = { 0 }; while(1) { data[0] = 1; for(int i=1;i<16;i++) data[i] += 1; axi_master_0->burst_write(OFFSET_DDR, 16, (int*)data); } }
producer0.h
#ifndef PRODUCER0_H_ #define PRODUCER0_H_ #include "systemc" using namespace sc_core; using namespace std; #include "AXI4_if.h" class producer0: public sc_core::sc_module { public: SC_HAS_PROCESS(producer0); sc_core::sc_in< bool > clock; sc_core::sc_in< bool > reset; AXI4M_bus_port< int > axi_master_0; producer0(sc_core::sc_module_name name); void thread(); }; #endif
The error is the following:
INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining loop 'memcpy.producer0.axi_master_0.m_if.Val.data.gep'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3. WARNING: [SCHED 204-69] Cannot apply resource constraint between nodes '' and '' due to unknow reason. WARNING: [SCHED 204-69] Cannot apply resource constraint between nodes '' and '' due to unknow reason. WARNING: [SCHED 204-69] Cannot apply resource constraint between nodes '' and '' due to unknow reason. WARNING: [SCHED 204-69] Cannot apply resource constraint between nodes '' and '' due to unknow reason. WARNING: [SCHED 204-69] Cannot apply resource constraint between nodes '' and '' due to unknow reason. WARNING: [SCHED 204-69] Cannot apply resource constraint between nodes '' and '' due to unknow reason. WARNING: [SCHED 204-69] Cannot apply resource constraint between nodes '' and '' due to unknow reason. WARNING: [SCHED 204-69] Cannot apply resource constraint between nodes '' and '' due to unknow reason. WARNING: [SCHED 204-69] Cannot apply resource constraint between nodes '' and '' due to unknow reason. WARNING: [SCHED 204-69] Cannot apply resource constraint between nodes '' and '' due to unknow reason. WARNING: [SCHED 204-69] Cannot apply resource constraint between nodes '' and '' due to unknow reason. WARNING: [SCHED 204-69] Cannot apply resource constraint between nodes '' and '' due to unknow reason. WARNING: [SCHED 204-69] Cannot apply resource constraint between nodes '' and '' due to unknow reason. WARNING: [SCHED 204-69] Cannot apply resource constraint between nodes '' and '' due to unknow reason. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 28.859 seconds; current allocated memory: 95.070 MB. INFO: [HLS 200-434] Only 1 loops out of a total 3 loops have been pipelined in this design. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. ERROR: [BIND 205-201] The memory core 'RAM' has insufficient ports, for array 'data' in function 'producer0::thread'
11-28-2019 08:14 PM
HI @hguerard ,
Yes, I was able to look into it. But somehow I missed to share my observations.
It seems the RAM error was occurring due to the while loop {while (1)}, changing the while loop to use for loop {for ( ; ; )} resolves the error and synthesizes the design without any errors.
11-06-2019 01:12 AM
Hi @hguerard ,
Can you please share the directives which you are using for the above code ?
11-06-2019 05:18 AM
Hi @shameera,
There is no directive.
11-06-2019 05:40 AM
threads? HLS? could you explain how you plan to use threads in hardware?
11-06-2019 05:47 AM
This is only the method name. It is not a std::thread nor a posix thread. On the other hand, this is a SystemC module with a SC_CTHREAD which is supported by Vivado HLS. Read page 354 of UG902.
11-06-2019 05:58 AM
Hi @hguerard ,
Can you please share the producer0.h file ?
11-06-2019 06:10 AM
11-06-2019 06:41 AM
This:
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3
ERROR: [BIND 205-201] The memory core 'RAM' has insufficient ports, for array 'data' in function 'producer0::thread'
makes me think you are asking the synthesis to do more things in parallel than possible with a dual(?) port RAM buffer.
11-06-2019 07:30 AM
I did not instruct HLS to pipeline the for-loop. It is doing this by his own means. The config_compile command does not specify to automatically pipeline for-loop.
To feed the discussion, this simplified for-loop (which does not use dual-port RAM) outputs the same log.
data[0] = 0; for(int i=1;i<16;i++) data[i] = 1;
My end goal is to somehow read a seed and initialize the first element of the array with it as such:
seed = 0; /* somehow read the seed */ data[0] = seed; for(int i=1;i<16;i++) data[i] = data[i-1] + 1;
But no matter I iterates over the array, I always stumble over the same warning and error.
To overcome the dual-port problem, I tried to partition the array with #pragma HLS array_partition variable=data complete but the HLS really chokes on it (complains about a json file wrongly generated):
ERROR: [HLS 200-445] Unexpected error generating RTL model: generate_json error: error "not well-formed (invalid token)" at line 46 character 44 "ster_0.m_if.Val.data[ <--Error-- 0]>
11-06-2019 08:29 AM
You wrote no directives, you didn't constrain HLS to II=1, but there it is doing it.
And you have SystemC stuff in HLS that is "supported" (I've heard that so many times and then...)
The very first thing I would do is to write that thing in HLS and forget about fancy threads. I bet is not even 100 lines. You may now that piece of advice 'Keep It Simple'
11-06-2019 08:38 AM
My guess is the for-loop being pipelined is somewhere under Xilinx's implementation of the AXI4M_bus_port class.
I pretty sure if I write pure C HLS code, I can get this thing working. However, in our design flow, we use a CAD tool that outputs SystemC module for Vivado HLS.
11-06-2019 08:52 AM - edited 11-06-2019 08:53 AM
Hi @hguerard ,
I am getting the below error when trying to synthesize the shared code
INFO: [HLS 200-489] Unrolling loop with tag "__ssdm_reset__"in function 'producer0::thread' completely with a factor of 15.
ERROR: [XFORM 203-801] Interface parameter 'producer0.axi_master_0.m_if.Val' must have the same bitwidth with the local buffer.
ERROR: [HLS 200-70] Pre-synthesis failed.
I tried it in HLS 2019.2 , can you please share the HLS version you are using ?
11-06-2019 09:03 AM - edited 11-06-2019 09:04 AM
I am using Vivado HLS 2018.3. Note that I have modified the original post to include a zip file that contains all the files.
Below is the TCL script used to create and do the synthesis of the project:
open_project hls_project add_files producer0.cpp open_solution "solution1" set_part {xc7z020clg484-1} create_clock -period 10.0 set_clock_uncertainty 3.0 config_rtl -reset_level high csynth_design exit
11-13-2019 06:45 AM
@shameera did you have the chance to try it with HLS 2018.3 ?
11-13-2019 09:15 PM
Hi @hguerard ,
I tried in HLS 2018.3 too, but still I see the same error which I had mentioned in my last post.
ERROR: [XFORM 203-801] Interface parameter 'producer0.axi_master_0.m_if.Val' must have the same bitwidth with the local buffer.
Here I have attached the HLS files for your reference. Use the command Vivado_hls -f ./build.tcl for building the project.
11-14-2019 05:56 AM
@shameera I have execute your tcl script but I have a totally different output. The main different is I am running on Windows 10 64-bit and you appear to be running under CentOS.
I have attached the generated Vivado HLS + log under Windows 10 with Vivado HLS 2018.3. What would you suggest from this point ?
11-15-2019 07:09 AM
Hi @shameera,
I run the project under a VM Ubuntu 64 bit and I have the same issue as you noted. To make it work, you have to change the line unsigned long data[16] = { 0 }; for int data[16] = { 0 };
Anyhow, I have added the modified source file with this post.
With this modification, you will be able to reproduce the initial error.
11-27-2019 07:01 AM - edited 11-27-2019 07:01 AM
@shameera were you able to test this zip file ?
11-28-2019 08:14 PM
HI @hguerard ,
Yes, I was able to look into it. But somehow I missed to share my observations.
It seems the RAM error was occurring due to the while loop {while (1)}, changing the while loop to use for loop {for ( ; ; )} resolves the error and synthesizes the design without any errors.
11-29-2019 05:18 AM