10-10-2013 03:59 AM
I got a problem during RTL export for the IP Catalog in HLS 2013.2.
When I add the following directive to the toplevel function
#pragma HLS RESOURCE variable=return core=AXI4LiteS
#pragma HLS INTERFACE ap_ctrl_hs register port=return
to be able to set the ap_start signal by the PS in a Zynq system and also let HLS generate an interrupt port for the IP Module I get the following message in the console window:
I [SYN-201] Setting up clock 'default' with a period of 10ns.
@I [HLS-10] Setting target device to 'xc7z020clg484-1'
@I [IMPL-8] Exporting RTL as an IP in IP-XACT.
"export_design -format ip_catalog -description "An IP generated by Vivado HLS" -vendor "xilinx.com" -library "hls" -version "1.0""
(file "C:\temp\HLS_testdesign\solution9\export.tcl" line 8)
@I [LIC-101] Checked in feature [VIVADO_HLS]
and only the driver part of the exported IP is generated. The RTL part is completely missing.
When I select "Pcore for EDK" instead, the driver and the RTL part is generated, although the driver code seems to contain some errors (e.g. the generated HLS_testdesign_sinit.c contains a reference to HLS_testdesign_Configtable , which not declared in the generated files)
If I remove the directives mentioned above the export works, but I don't get the interrupt output and have to start the IP by an GPIO for example.
Has anyone an idea what's wrong with the IP Catalog RTL export or encountered similar problems?
10-10-2013 05:41 AM
Seems some errors occur, however, the reason is not shown.
Is it able to attach your code here?
10-30-2013 05:06 AM
10-31-2013 01:50 AM
I still have the problem with the new 2013.3 HLS Version.
But I think I found a solution while I was preparing a testcase for the Xilinx support. (Unfortunately I'm not able to provide the original code)
The problem seems to be related to long file, function and or path names of the file I tried to process with HLS.
The original code uses a file named similar to Hls_abcdefghijklmnopqrstuvwxyzabcdefghijklmn.cpp (the target function is named accordingly)
When I prepared the testcase I only renamed the file to IpCatalogTestCase.cpp...and suddenly it worked.
Unfortunately, up to now I was not able to generate a testcase by increasing the file name length successively till I can reproduce the error
But I think a possible solution is to shorten the file and function name.
During my file name length experiments I encountered a new error with the 2013.3 HLS Version (while exporting the generated IP)
@E [RTMG-101] Couldn't open "Hls_abcdefghijklmnopqrstuvwxyzabcdefghijklmn_ap_rst_if.v": no such file or directory
"export_design -format ip_catalog -description "An IP generated by Vivado HLS" -vendor "xilinx.com" -library "hls" -version "1.00.a""
(file "C:/temp/Vivado_HLS_Tutorial/Hls_abcdefghijklmnopqrstuvwxyzabcdefghijklmn/Hls_abcdefghijklmnopqrstuvwxyzabcdefghijklmn/solution1/export.tcl" line 8)
I enclosed the zipped HLS Test Project.
10-31-2013 02:35 AM
02-21-2020 06:30 AM
the RTL_Export with VHDL and "IP Catalog" option is not working anymore on my VIVADO HLS 2018.2_AR71409
even if running it as administrator.
One month ago, on this same project it was working.
How to fix this ?