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Visitor
Visitor
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Registered: ‎09-06-2017

HLS tutorial UG871 (v2016.4) ch10 lab2 problem

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Hi, I'm following the vivado HLS  2016.4 tutorial UG871 and downloaded files for ch10 lab2:

Streaming Data Between the Zynq CPU and HLS Accelerator Blocks

without chaning any code and procedure( use as it is). 

When run vivado_hls -f run_hls.tcl, I got error message like:

 INFO: [HLS 200-111] Finished Pre-synthesis Time (s): cpu = 00:00:23 ; elapsed = 00:02:55 . Memory (MB): peak = 602.367 ; gain = 553.039
WARNING: [XFORM 203-631] Renaming function 'Loop_realfft_be_stream_output_proc' (./xfft2real.h:121:37) into Loop_realfft_be_stre.
WARNING: [XFORM 203-631] Renaming function 'Loop_realfft_be_rev_real_hi_proc' (./xfft2real.h:116:37) into Loop_realfft_be_rev_.
WARNING: [XFORM 203-631] Renaming function 'Loop_realfft_be_descramble_proc' (./xfft2real.h:88:37) into Loop_realfft_be_desc.
WARNING: [XFORM 203-631] Renaming function 'Loop_realfft_be_buffer_proc' (./xfft2real.h:64) into Loop_realfft_be_buff.
ERROR: [XFORM 203-801] Interface write on 'dout.V.data' has incompatible types. Possible cause(s): data pack is only applied on source(variable) or destination(port).
ERROR: [HLS 200-70] Failed building synthesis data model.
command 'ap_source' returned error code
while executing
"source [lindex $::argv 1] "

 

Any update to the example code/procesure (seen most examples using older version of vivado hls)? Has anyone seen the same issue, any workaround?

 

Thanks,

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Visitor
Visitor
2,786 Views
Registered: ‎09-06-2017

removing the DATA_PACK pragma resolves the problem: as mentioned in some threads, the HLS seemly auto packed AXI-stream struct/parameters; just curious how it worked in older version demo/tutorial.

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Moderator
Moderator
2,079 Views
Registered: ‎09-15-2016

Hi @jinming_ge,

 

You can try this:

- Visit this webpage.

- Click on "See all versions" below UG871 description.

- Download the reference files associated with latest Vivado and check if the particular file helps.

 

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Visitor
Visitor
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Registered: ‎09-06-2017

Hi,

I'm using UG871 - Vivado Design Suite Tutorial: High-Level Synthesis ( ver2016.4, 11353 KB ) [PDF] and Associated File(s)

Are you suggesting newer version?

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Visitor
Visitor
2,044 Views
Registered: ‎09-06-2017

The problem can be reproduced with 2017.1 version (same version of Vivado Design Suite and UG871 Associated Files)

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Visitor
Visitor
2,787 Views
Registered: ‎09-06-2017

removing the DATA_PACK pragma resolves the problem: as mentioned in some threads, the HLS seemly auto packed AXI-stream struct/parameters; just curious how it worked in older version demo/tutorial.

View solution in original post