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MGaber123
Visitor
Visitor
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Registered: ‎11-17-2020

Hls warning synthesis

I get this warning please any hint to solve this problem

WARNING: [XFORM 203-713] All the elements of global array 'lineBuff.val[0]' should be updated in process function 'doImgProc244_Loop_2_proc78', otherwise it may not be synthesized correctly

 

// Defining the line buffer and setting the inter dependency to false through pragmas
hls::LineBuffer<KERNEL_DIM1_2,IMG_HEIGHT_OR_ROWS_PADDING_2,float24_t> lineBuff[CHANNEL_SIZE_2];
hls::Window< KERNEL_DIM1_2,KERNEL_DIM1_2, float24_t> window [BATCH_SIZE_2][CHANNEL_SIZE_2];


//hls::stream<float24_t> inStream2;
// Index used to keep track of row,col
int idxCol = 0;
int idxRow = 0;
int pixConvolved = 0;
//float24_t dataOut[IMG_WIDTH_OR_COLS*IMG_HEIGHT_OR_ROWS]={0};
float24_t currPixel;
float24_t val ;
float24_t valOutput;
float24_t pixelIn=0;
float24_t temp_val=0;


//float24_t dataOut[IMG_WIDTH_OR_COLS*IMG_HEIGHT_OR_ROWS]={0};

for (int idxPixel = 0; idxPixel < (IMG_HEIGHT_OR_ROWS_PADDING_2*IMG_HEIGHT_OR_ROWS_PADDING_2); idxPixel++)
{
for(int i=0;i<CHANNEL_SIZE_2;i++)
{ currPixel = outputStream1.read();
lineBuff[i].shift_up(idxCol);
lineBuff[i].insert_top(currPixel,idxCol);
}
for (int j=0;j<BATCH_SIZE_2;j++)
{
// #pragma HLS PIPELINE
valOutput=0;
for (int i=0;i<CHANNEL_SIZE_2;i++)
{
//#pragma HLS UNROLL

for (int idxWinRow = 0; idxWinRow < KERNEL_DIM1_2; idxWinRow++)
{
for (int idxWinCol = 0; idxWinCol < KERNEL_DIM1_2; idxWinCol++)
{
temp_val = (float24_t)lineBuff[i].getval(idxWinRow,idxWinCol+pixConvolved);
val = (float24_t)kernel[j][i][(idxWinRow*KERNEL_DIM1_2) + idxWinCol ] * temp_val;
window[j][i].insert(val,idxWinRow,idxWinCol);

}

 

this part of my code that i used line buffer 

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aoifem
Moderator
Moderator
234 Views
Registered: ‎11-21-2018

Hi @MGaber123 

This seems to be a similar issue to your other post: 
https://forums.xilinx.com/t5/High-Level-Synthesis-HLS/HLS-warning-during-synthesis/td-p/1174710

Could you try updating the library as I suggested in your other post, and let me know if it solves the issue. 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA


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