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Explorer
Explorer
1,937 Views
Registered: ‎03-29-2017

How to Reduce LUT utilization in a Vivado HLS design?

Hi,

 

 

I need help in reducing the utilization numbers of a design within the confines of HLS (i.e. can't just redo the design in an HDL). I am targeting the KC board.

 

Could someone please provide a few suggestions as to how I can reduce the LUT utilization.

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3 Replies
Voyager
Voyager
1,879 Views
Registered: ‎06-24-2013

Re: How to Reduce LUT utilization in a Vivado HLS design?

Hey @thaus_015,

 

Could someone please provide a few suggestions as to how I can reduce the LUT utilization.

Depending on what causes your LUT utilization, the following might work ...

  • Force distributed memory into Block RAM
  • Force operations (add/sub/mul) into DSP Blocks
  • Reduce throughput and increase per cycle delay
  • Prevent loop unrolling

Hope this helps,

Herbert

-------------- Yes, I do this for fun!
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Explorer
Explorer
1,852 Views
Registered: ‎03-29-2017

Re: How to Reduce LUT utilization in a Vivado HLS design?

Thanks for your response. I am new into VIVADO. So can you share any example design.

 

Because, Its all very new to me

 

  • Force distributed memory into Block RAM
  • Force operations (add/sub/mul) into DSP Blocks
  • Reduce throughput and increase per cycle delay
  • Prevent loop unrolling

Thanks

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Moderator
Moderator
1,783 Views
Registered: ‎06-24-2015

Re: How to Reduce LUT utilization in a Vivado HLS design?

@thaus_015

 

You can use any of Xilinx's example designs provided with HLS, or the design that you are currently working on.

All you need to do is apply RESOURCE directives on the block(be it memory or operations like addition and multiplication)

Refer Table 1-14, 1-15 and 1-16 page 179(onwards) to refer the list of functional, floating-point and storage cores that can be used with the RESOURCE directive: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_3/ug902-vivado-high-level-synthesis.pdf 

Thanks,
Nupur
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