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jerhill
Observer
Observer
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Registered: ‎07-18-2019

How to communicate with IP in Vitis using various number types.

I have constructed a IP block in Vitis_HLS that has inputs and outputs of various types, including ap_fixed, complex<ap_fixed>, double, and signed and unsigned integers transmitted via AXI4-Lite interfaces. Building and testing this in Vitis_HLS is fairly straightforward.

After synthesizing the IP and building a platform in Vitis, though, I am a bit frustrated. The AXI functions require u64 words for all writes and reads except for the complex ones, which use structures of four u32 words each. Are there functions that allow me to do a straightforward conversion, so that I can, for example, take a double variable and generate the appropriate 64-bit integer that my IP would interpret as the double that it is expecting?

That is, given variables like

double fin = 3.14;
double din = 6.28;
int iin = -25;
double complex xin = 1.5 + I * 2.5;

and the functions

typedef struct {
u32 word_0;
u32 word_1;
u32 word_2;
u32 word_3;
} XTestfunc_Xin;

void XTestfunc_Set_fin(XTestfunc *InstancePtr, u64 Data);
void XTestfunc_Set_din(XTestfunc *InstancePtr, u64 Data);
void XTestfunc_Set_iin(XTestfunc *InstancePtr, u64 Data);
void XTestfunc_Set_xin(XTestfixed *InstancePtr, XTestfunc_Xin Data);

how do I mangle the variables to create u32 and u64 variables that my IP would recognize since (from Vitis_HLS) it is expecting them to be particular types? For example,

ap_fixed<64,32> fin;
double din;
int iin;
hls::x_complex<ap_fixed<64,32>> xin;

Similarly, I need to know how to take a u64 from the IP and generate an appropriate value and type. I'm sure I can reverse-engineer this thing with some time and effort, but that would be a pain, and I can't be the first person to run into this. I haven't been able to find anything relevant online.

Thanks for your assistance!

-JMH

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aoifem
Moderator
Moderator
200 Views
Registered: ‎11-21-2018

Hi @jerhill 

This feature is supported in Vitis HLS 2020.2: 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug1399-vitis-hls.pdf

aoifem_0-1615538159577.png

 

You could also try the following: 

1. If you are trying to get 64 bits of data on a 32 bit AXI4-LITE interface, this will not work as it will take two transactions (burst of 2) and AXI4-LITE does not support burst.  If you went AXI4 FULL then you could do a burst of 2 on the 32 bit interface. So, I think you would need an AXI4 full interface that supports bursting.

2. The AXI Interconnect IP can also convert from 32 to 64. 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA


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