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Visitor kvraju02
Visitor
9,421 Views
Registered: ‎03-26-2014

How to create two clocks one for ctrl signal other one for data ports

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Hi All,

we want to two separate clocks one for ctrl bus and other one for data .

by default the "vivado_hls" IP has control bus clock port.

Can we create two saperate clocks in HLS?  like contrl bus(AXI4-Lite) used as 50MHz and other data ports(AXI4-Stream) used as 150MHz  ?

Could you please suggestion us with small snippet code  or reference document .

 

Thanks and Regards,

Raju

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Moderator
Moderator
14,504 Views
Registered: ‎04-17-2011

Re: How to create two clocks one for ctrl signal other one for data ports

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@kvraju02 Do you still have any further question on this topic? If you found any of the above post useful then you can accept it as a solution. It is a good forums practice.

Regards,
Debraj
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Moderator
Moderator
9,405 Views
Registered: ‎04-17-2011

Re: How to create two clocks one for ctrl signal other one for data ports

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For C and C++ designs, only a single clock is supported. For SystemC designs, multiple named clocks can be created and applied to different SC_MODULEs using the set_directive_clock command.
Regards,
Debraj
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Xilinx Employee
Xilinx Employee
9,402 Views
Registered: ‎08-17-2011

Re: How to create two clocks one for ctrl signal other one for data ports

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for the C/C++ designs, if you connect the slow clock domain to the VHLS IP the tools should introduce the necessary circuits for clock rate conversion in the axi interconnect. that's the theory; I haven't tested in practice.
- Hervé

SIGNATURE:
* New Dedicated Vivado HLS forums* http://forums.xilinx.com/t5/High-Level-Synthesis-HLS/bd-p/hls
* Readme/Guidance* http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

* Please mark the Answer as "Accept as solution" if information provided is helpful.
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Moderator
Moderator
14,505 Views
Registered: ‎04-17-2011

Re: How to create two clocks one for ctrl signal other one for data ports

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@kvraju02 Do you still have any further question on this topic? If you found any of the above post useful then you can accept it as a solution. It is a good forums practice.

Regards,
Debraj
----------------------------------------------------------------------------------------------
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Give Kudos to a post which you think is helpful and reply oriented.
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View solution in original post

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Visitor kvraju02
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9,391 Views
Registered: ‎03-26-2014

Re: How to create two clocks one for ctrl signal other one for data ports

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Hi debrajr,

Thanks a lot for your response.

Thanks and Regards,
Raju
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8,816 Views
Registered: ‎02-05-2014

Re: How to create two clocks one for ctrl signal other one for data ports

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Hi,

 

I've designed image processing algorithms with Vivado HLS.

 

Now I'm using Vivado to integrate my IP. I'm using one AXI stream input and several AXI Master ports that read and write in DDR.

 

I have also a AXILite port for IP control.In my design I have 2 differents clock frequencies: 50MHh for AXILite and 150 Mhz for others.

 

But after the Vivado HLS generation there is just one "aclk" port in my IP. When I'm tying to plug to 50Mhz, Vivado tells me I can't because my AXI Master are 150Mhz clocked.

 

My question is: it's possible to have 2 port in my Vivado HLS IP,  "s_axi_lite_aclk" and "m_axi_master_aclk"? I'm design in C, C++.

 

And if it's not possible how to resolve my problem?

 

Thanks

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Moderator
Moderator
8,684 Views
Registered: ‎04-17-2011

Re: How to create two clocks one for ctrl signal other one for data ports

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@maxime.pottier Please create a new topic for your query. 

Regards,
Debraj
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