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anjf
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Registered: ‎06-18-2014

How to descript a Dual Port RAM in SystemC

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I have writen a ram like this:


#define DATA_WIDTH        8
#define ADDR_WIDTH        8
#define RAM_DEPTH         1 << ADDR_WIDTH

SC_MODULE (ram_dp_ar_aw) {
    sc_in    <bool> clk;
    sc_in    <sc_uint<ADDR_WIDTH> > address_0;
    sc_in    <bool> cs_0 ;
    sc_in    <bool> we_0 ;
    sc_in    <bool> oe_0  ;
    sc_in    <sc_uint<ADDR_WIDTH> > address_1;
    sc_in    <bool> cs_1 ;
    sc_in    <bool> we_1 ;
    sc_in    <bool> oe_1  ;
    sc_in <sc_uint<DATA_WIDTH> > data_in_0;
    sc_in <sc_uint<DATA_WIDTH> > data_in_1;
    sc_out <sc_uint<DATA_WIDTH> > data_out_0;
    sc_out <sc_uint<DATA_WIDTH> > data_out_1;

    //-----------Internal variables-------------------
    sc_signal <sc_uint <DATA_WIDTH> > mem [RAM_DEPTH];

    //-----------Methods------------------------------
    void  READ_0 ();
    //-----------Constructor--------------------------
    SC_CTOR(ram_dp_ar_aw) {
        SC_METHOD (READ_0);
        sensitive_pos << clk;
    }
};

 

void  ram_dp_ar_aw::READ_0 () {
  data_out_0 = mem[address_0.read()];
  data_out_1 = mem[address_1.read()];
  if (cs_0.read() && we_0.read()) {
    mem[address_0.read()] = data_in_0.read();
  }
  if (cs_1.read() && we_1.read()) {
    mem[address_1.read()] = data_in_1.read();
  }
}

How ever, the synthesis results show it will use 2 cycles to read&write.

Can I add some constraints to make it become a Dual Port RAM?

 

Screenshot from 2014-07-18 16:13:12.png

Screenshot from 2014-07-18 16:14:13.png

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tessitd
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11,082 Views
Registered: ‎11-13-2009

So the memory is clocked and you have a register on the output?  2 cycles is what you should expect?

 

Is the problem the read or the write?  The read is correct because of above.  The Write seems to be 1 cycle if I interprete the report correctly.

 

In a past life I spent considerable time optomizing SystemC (using Forte DA) to product tight memory cycles.  The code ended up looking like Verilog but it functioned to the maximum speed available in the FPGA I had available.  Lets just say to make it work correctly I had to have a 4x clock against my system clock running at 1x.  If your read requirements are less than 2 clocks then you might consider doubling your clock to access the memory.

 

TomT...

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tessitd
Explorer
Explorer
11,083 Views
Registered: ‎11-13-2009

So the memory is clocked and you have a register on the output?  2 cycles is what you should expect?

 

Is the problem the read or the write?  The read is correct because of above.  The Write seems to be 1 cycle if I interprete the report correctly.

 

In a past life I spent considerable time optomizing SystemC (using Forte DA) to product tight memory cycles.  The code ended up looking like Verilog but it functioned to the maximum speed available in the FPGA I had available.  Lets just say to make it work correctly I had to have a 4x clock against my system clock running at 1x.  If your read requirements are less than 2 clocks then you might consider doubling your clock to access the memory.

 

TomT...

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anjf
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Registered: ‎06-18-2014

Comparing with SystemVerilog, SystemC is not suitable to write cycle acurate ciruits.

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