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Visitor
Visitor
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Registered: ‎06-09-2016

How to disable the use of IP block in Vivado HLS

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Hello, I am using Vivado HLS 2015.4 to convert a C code into a Verilog code. The C code has floating point operation, because of this, my output Verilog code contains some modules that use Xilinx's IP block.

 

I want to do something with this Verilog code without involving Xilinx's tool, so I do not want to deal with Xilinx's IP block, is there a way to tell Vivado HLS to generate Verilog code without involving Xilinx's IP block? Thank you. 

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Advisor
Advisor
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Registered: ‎04-26-2015

Re: How to disable the use of IP block in Vivado HLS

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I don't think there is such an option. It is annoying, because it means that I need to keep multiple versions of HLS blocks (eg. built in 2015.2 and 2015.4) to support different versions of Vivado, since a block built in HLS 2015.2 won't work in Vivado 2015.4 (floating-point core changed version) and vice versa. It'd be much nicer if you could force HLS to include absolutely everything that it requires inside the IP code, making the HDL code essentially generic and therefore future-proof.

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Advisor
Advisor
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Registered: ‎04-26-2015

Re: How to disable the use of IP block in Vivado HLS

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I don't think there is such an option. It is annoying, because it means that I need to keep multiple versions of HLS blocks (eg. built in 2015.2 and 2015.4) to support different versions of Vivado, since a block built in HLS 2015.2 won't work in Vivado 2015.4 (floating-point core changed version) and vice versa. It'd be much nicer if you could force HLS to include absolutely everything that it requires inside the IP code, making the HDL code essentially generic and therefore future-proof.

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Teacher
Teacher
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Registered: ‎03-31-2012

Re: How to disable the use of IP block in Vivado HLS

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>> block built in HLS 2015.2 won't work in Vivado 2015.4

I am not sure if this is true. The ip will stay locked but it will work in the newer version of the tools. I never had an issue, especially with the command line flow. The GUI just shows you the latest version but quite a bit of the earlier versions are available. For example I see floating_point_v7_0 and floating_point_v7_1 in 2016.1 which are the same versions as in 2015.4.
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Teacher
Teacher
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Registered: ‎03-31-2012

Re: How to disable the use of IP block in Vivado HLS

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Unfortunately some IP is quite valuable so I suspect Xilinx would be hesitant to make them available in verilog format. Floating point IP is encrypted so you can't even copy it to your system.

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-22-2011

Re: How to disable the use of IP block in Vivado HLS

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The IP for floating point is protected and there is no way to view the verilog.

 

Also, you said "I want to do something with this Verilog code without involving Xilinx's tool": the license agreement you clicked on, and agreed to obey, specifically prohibits this. The output of Vivado HLS can only be used with Xilinx tools. 

 

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Advisor
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Registered: ‎04-26-2015

Re: How to disable the use of IP block in Vivado HLS

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@muzaffer - I was having problems using a HLS block from 2015.2 under 2015.4 and 2016.1, although that was through the GUI. I see your point about the IP being protected, though. I suppose that HLS could package the floating-point IP (still encrypted) with the generated IP core, but that would probably cause all sorts of problems with having multiple versions of the same block in one project.

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Visitor
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Registered: ‎06-09-2016

Re: How to disable the use of IP block in Vivado HLS

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Oops, thank you so much for pointing this out. I am just doing this for study purpose, not for any commercial use or profit, such as see how good the HLS's verilog code is(e.g. area efficiency), is this not allowed?

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