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Adventurer
Adventurer
837 Views
Registered: ‎07-08-2019

How to force registering the output of a module?

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Hi,

I am new to Vivado HLS. I have a 2-level tree of 3 adders adding four input values. The inputs of adder tree are provided by four multiplexers.

float my_func(

       float a0, float a1, float a2, float a3,

       float b0, float b1, float b2, float b3,

       bool sel

) {

       float t0 = (sel) ? a0 : b0;

       float t1 = (sel) ? a1 : b1;

       float t2 = (sel) ? a2 : b2;

       float t3 = (sel) ? a3 : b3;

       return (t0+t1)+(t2+t3);

}

How can I force the outputs of MUXs (i.e. t0, t1, t2, t3) to be always registered independent from the clock frequency?

Thanks in advance

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1 Solution

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Xilinx Employee
Xilinx Employee
784 Views
Registered: ‎09-05-2018

Hey @akokha ,

You can register inputs and outputs using either the INTERFACE derictive or the config_interface settings. However, because t[0..3] are internal signals, you don't really have control over them.

You can use the static modifier to keep data in between function calls, and may result in registers, but since t[0..3] are updated every clock cycle, I don't see the point.

I would recommend you get away from the ideas of adder trees, multiplexers, and logic levels to some extent. That is the purpose behind Vivado HLS - to abstract out some of the details of the hardware. If you care, write RTL. Otherwise, write C and let HLS do the optimization for you:

#define SIZE 4
float my_func( float a[SIZE], float b[SIZE], bool sel ) {
#pragma HLS ARRAY_PARTITION variable=a complete
#pragma HLS ARRAY_PARTITION variable=b complete
  float retval = 0.0;
  if( sel ) {
    for( int i = 0 ; i < SIZE ; i ++ ) {
#pragma HLS UNROLL
      retval += a[i];
    }
  } else {
    for( int i = 0 ; i < SIZE ; i ++ ) {
#pragma HLS UNROLL
      retval += b[i];
    }
  }
  return retval;
}

This way, HLS will infer the same functionality but will be able to use more or fewer levels of logic to reduce utilization while reducing timing. If you want more control over the exact structure of the adder tree, you are probably better served by writing RTL inside Vivado.

Nicholas Moellers

Xilinx Worldwide Technical Support

View solution in original post

2 Replies
Highlighted
Xilinx Employee
Xilinx Employee
785 Views
Registered: ‎09-05-2018

Hey @akokha ,

You can register inputs and outputs using either the INTERFACE derictive or the config_interface settings. However, because t[0..3] are internal signals, you don't really have control over them.

You can use the static modifier to keep data in between function calls, and may result in registers, but since t[0..3] are updated every clock cycle, I don't see the point.

I would recommend you get away from the ideas of adder trees, multiplexers, and logic levels to some extent. That is the purpose behind Vivado HLS - to abstract out some of the details of the hardware. If you care, write RTL. Otherwise, write C and let HLS do the optimization for you:

#define SIZE 4
float my_func( float a[SIZE], float b[SIZE], bool sel ) {
#pragma HLS ARRAY_PARTITION variable=a complete
#pragma HLS ARRAY_PARTITION variable=b complete
  float retval = 0.0;
  if( sel ) {
    for( int i = 0 ; i < SIZE ; i ++ ) {
#pragma HLS UNROLL
      retval += a[i];
    }
  } else {
    for( int i = 0 ; i < SIZE ; i ++ ) {
#pragma HLS UNROLL
      retval += b[i];
    }
  }
  return retval;
}

This way, HLS will infer the same functionality but will be able to use more or fewer levels of logic to reduce utilization while reducing timing. If you want more control over the exact structure of the adder tree, you are probably better served by writing RTL inside Vivado.

Nicholas Moellers

Xilinx Worldwide Technical Support

View solution in original post

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Adventurer
Adventurer
762 Views
Registered: ‎07-08-2019

hey @nmoeller

Thank you for your perfect answer.

So, I must try to wrtie more high-level code as far as I can. Then, let Vivado choose best clock frequency and place necessary regs by trying different clock periods.

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