How to implement both SW trigger from AXI lite and HW trigger from the HLS interface in a design?

[nanson]

Hi, 

I'd like to implement a module in HLS which the behavior is like a random generator or oscillator. It has some programmable parameters and plans to bind to AXI slave lite interface. However, for the trigger or enable of the module to generate output, it can control from CPU via AXI lite bus or HW interface. Every time it triggers, it will generate some data samples for use. For CPU control interface, it's easier as a means for bringing up testing. In a real application, if a scenario needs to generate the data sample at a certain speed like 2KHz etc., it's a waste to exploit CPU. Therefore, I'm thinking to use other HW block to generate the trigger signals at a certain speed.

If that's the case, can AXI lite interface and the HW trigger signal exist in the module interface at the same time in HLS?

If yes, what compile directive would you suggest to use?

[nanson]

After some analysis, I found that it will have confliction in pragma assignment which assigns the same variable to two interface pragmas. Thus, it seems infeasible for the same variable to bring out two different interfaces by MUX switch.