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Adventurer
Adventurer
713 Views
Registered: ‎02-24-2019

How to optimize the speed to write static array in a loop?

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Below  is a very simple function. However, as every loop take 100ps to run, a simple loop of 10 will result in a very large latencies.

How can I speed it up?

 

static int vals_dst[200];
void hole_filling(int x1,  int loop,  int val, int vals_dst[dst_cols])
{
DDX_LOOP:
for(int idx=0; idx<loop;idx++)
         vals_dst[idx] = val;
}

 

Eli

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Advisor
Advisor
546 Views
Registered: ‎04-26-2015

Each iteration takes 100ps to run? So your FPGA is running at >10GHz? That seems highly unlikely...

 

Unless vals_dst is fully partitioned (so you can unroll the loop completely and do the whole lot in one cycle), this is going to be slow. You might need to look at how the rest of the system is designed to try to eliminate this loop.

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Moderator
Moderator
596 Views
Registered: ‎05-31-2017

HI @eewse ,

Have you tried using array partition & using unrolling to your code ? This may improve the performance and also there will be increase in hardware resources.

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Adventurer
Adventurer
585 Views
Registered: ‎02-24-2019

I have tried both array practition and loop unroll, (correct me if I am wrong) I find that it might improve the throughput but the latencies do not change much.

 

 

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Advisor
Advisor
547 Views
Registered: ‎04-26-2015

Each iteration takes 100ps to run? So your FPGA is running at >10GHz? That seems highly unlikely...

 

Unless vals_dst is fully partitioned (so you can unroll the loop completely and do the whole lot in one cycle), this is going to be slow. You might need to look at how the rest of the system is designed to try to eliminate this loop.

View solution in original post