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Contributor
Contributor
677 Views
Registered: ‎05-08-2019

How to perform 32 bit integer addition operation in vivado hls with 400Mhz?

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I need to implement 32 bit integer addition in my project. It is working fine for target frequency of 250Mhz. But when i increase 400Mhz it is not working fine causing negative slack. Please assist me in implementing 32bit integer addition with 400Mhz. Is there any pragma for the that? Thank you

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1 Solution

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Scholar dgisselq
Scholar
455 Views
Registered: ‎05-21-2015

Re: How to perform 32 bit integer addition operation in vivado hls with 400Mhz?

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@chandu_sathi,

Pardon the Verilog in an HLS forum, but here's how I would turn a 32-bit add into two 16-bit adds.

reg [31:0] pipeline;
reg carry;

always @(posedge clk)
begin
  /// First clock
  { carry, pipeline[15:0] } <= input_a[15:0] + input_b[15:0];
  pipeline[31:16] <= input_a[31:16] + input_b[31:16];

  /// Second clock
  output_val <= pipeline + (carry << 16);
end

Another approach is the one I used for this project that needed to count clocks across clock domains.  That is, from a 100MHz clock domain, can you count the number of clocks per second and report the result?  I seem to recall at one time seeing a result as high as 400MHz, but it's been a while as I don't normally go up that high.  Might work nicely for radiometric counts, though, although it does lose some of the lower bits in the processing.

Dan

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12 Replies
Scholar drjohnsmith
Scholar
641 Views
Registered: ‎07-09-2009

Re: How to perform 32 bit integer addition operation in vivado hls with 400Mhz?

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You have to remember your designing hardware , and the hardware has limits,
some FPGAs just wont run at 400 MHz,

you need to look at the algorithm your implementing in the hardware, look at the schematic produced, to see what the HLS is generating,

Have you included sufficient pipe lining in the design ? could you use ping pong when you have two adders , each running at half the rate, and use them alternatively , that gives twice the throughput with an extra register delay,

does you device have DSP blocks,

there is no magic button that can be used to overcome a design that can be improved,


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Contributor
Contributor
625 Views
Registered: ‎05-08-2019

Re: How to perform 32 bit integer addition operation in vivado hls with 400Mhz?

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Thanks for the reply. I am using VCU108 ultrascale fpga. It has DSP in it. I am getting critical path issue at high frequencies.

for(int j=1;j<=64;j++)
{
#pragma HLS PIPELINE
(tmp2,tmp1)=X[j-1]*Y[i];
(tmp4,tmp3)=q*M[j-1];
delta0=tmp2 + tmp4;
(tmp2,tmp1)=X[j]*Y[i];
(tmp4,tmp3)=q*M[j];
delta1=delta0+tmp1+tmp3;
delta2=delta1+SM[j] + C;
(C,SM[j-1])=delta2;
}

WARNING: [SCHED 204-21] The critical path in module 'mod_mult_2048' consists of the following:
'load' operation ('SM_63_V_load_1', sesha_pcie_encry/paillier.cpp:56) on local variable 'SM[63].V' [555] (0 ns)
'mux' operation ('SM_V_load_2_phi', sesha_pcie_encry/paillier.cpp:56) [637] (1.52 ns)
'add' operation ('tmp3', sesha_pcie_encry/paillier.cpp:56) [640] (1.47 ns)
'add' operation ('delta2.V', sesha_pcie_encry/paillier.cpp:56) [647] (1.47 ns)
'phi' operation ('C.V', sesha_pcie_encry/paillier.cpp:45) with incoming values : ('p_Result_3_cast', sesha_pcie_encry/paillier.cpp:45) ('tmp_4', sesha_pcie_encry/paillier.cpp:57) [416] (0 ns)
'add' operation ('tmp5', sesha_pcie_encry/paillier.cpp:56) [642] (1.47 ns)
'add' operation ('tmp4', sesha_pcie_encry/paillier.cpp:56) [644] (1.47 ns)

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Scholar drjohnsmith
Scholar
576 Views
Registered: ‎07-09-2009

Re: How to perform 32 bit integer addition operation in vivado hls with 400Mhz?

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how are you expecting bit width to change over the operation ?

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Contributor
Contributor
566 Views
Registered: ‎05-08-2019

Re: How to perform 32 bit integer addition operation in vivado hls with 400Mhz?

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Thanks for the reply sir. The code that I have attached is 32 bit radix operands. The implemented code is working for frequency below 140 MHzs. But when I am trying to increase frequency above this, the code is getting critical path issue. I have read in some research publications that usually 8-bit addition can operate till 400 MHzs and 32-bit addition takes around 250 MHzs . But, my design has some requirement of using 32 bit width radix size words . I have attached my design privately to you. I want to know, maximum frequency of my design that it can operate efficiently without any critical timing issues. I am trying to improvise the design but I am not getting better performance at frequencies higher than 140 MHzs. In my project the higher frequency is important because throughput is dependent on frequency. Maximum frequency gives high throughput. I am new to this vivado tools. Please assist me in this. Thank you.

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Xilinx Employee
Xilinx Employee
554 Views
Registered: ‎09-04-2017

Re: How to perform 32 bit integer addition operation in vivado hls with 400Mhz?

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Hi,

  You should probably add some pipelines to break the path. 

Thanks,

Nithin

Contributor
Contributor
511 Views
Registered: ‎05-08-2019

Re: How to perform 32 bit integer addition operation in vivado hls with 400Mhz?

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Hi,

Thanks for the reply. If you don't mind, can u explain with simple example how to add pipelines? Thank you

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Scholar dgisselq
Scholar
456 Views
Registered: ‎05-21-2015

Re: How to perform 32 bit integer addition operation in vivado hls with 400Mhz?

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@chandu_sathi,

Pardon the Verilog in an HLS forum, but here's how I would turn a 32-bit add into two 16-bit adds.

reg [31:0] pipeline;
reg carry;

always @(posedge clk)
begin
  /// First clock
  { carry, pipeline[15:0] } <= input_a[15:0] + input_b[15:0];
  pipeline[31:16] <= input_a[31:16] + input_b[31:16];

  /// Second clock
  output_val <= pipeline + (carry << 16);
end

Another approach is the one I used for this project that needed to count clocks across clock domains.  That is, from a 100MHz clock domain, can you count the number of clocks per second and report the result?  I seem to recall at one time seeing a result as high as 400MHz, but it's been a while as I don't normally go up that high.  Might work nicely for radiometric counts, though, although it does lose some of the lower bits in the processing.

Dan

View solution in original post

Scholar drjohnsmith
Scholar
425 Views
Registered: ‎07-09-2009

Re: How to perform 32 bit integer addition operation in vivado hls with 400Mhz?

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Sorry , though I can see why you emailed it to me, for the good of the community I do not reply to email help.
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Scholar drjohnsmith
Scholar
422 Views
Registered: ‎07-09-2009

Re: How to perform 32 bit integer addition operation in vivado hls with 400Mhz?

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try this

https://www.xilinx.com/html_docs/xilinx2017_4/sdaccel_doc/fde1504034360078.html

do you not have to say what you want pipeined by how much ?

I do have to ask, why are you using HLS ? 

 

 

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Contributor
Contributor
264 Views
Registered: ‎05-08-2019

Re: How to perform 32 bit integer addition operation in vivado hls with 400Mhz?

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@drjohnsmith sorry for late reply. I am new to this vivado tools . Can't i achieve high frequency using hls? 

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Scholar drjohnsmith
Scholar
251 Views
Registered: ‎07-09-2009

Re: How to perform 32 bit integer addition operation in vivado hls with 400Mhz?

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If the FPGA can meet th espeed , and it should , then you can

 

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Moderator
Moderator
182 Views
Registered: ‎05-31-2017

Re: How to perform 32 bit integer addition operation in vivado hls with 400Mhz?

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Hi @chandu_sathi ,

If your query has been answered or your issue is solved, can you please kindly mark the response which helped as a solution (click on "Accept as solution" button below the reply) ?

If the issue is not solved/answered, please reply to this thread giving more information on your current status.

 

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