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3,096 Views
Registered: ‎08-22-2017

How to pipeline a loop which contains a FIR IP?

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The user guide file UG902 says that the FIR IP cannot be pipelined. However I have a work which must pipeline the FIR IP to meet the latency. Is there anyone can give me some advices? Thanks!
The following is my test codes.
===My Codes====================================================
// DUT
void fir_top_3chnls(s_data_t in[INPUT_LENGTH*3],
             m_data_t out[OUTPUT_LENGTH*3],
             config_t* config_dummy)
{
#pragma HLS interface ap_fifo depth=INPUT_LENGTH port=in
#pragma HLS interface ap_fifo depth=OUTPUT_LENGTH port=out
#pragma HLS stream variable=in
#pragma HLS stream variable=out
    s_data_t fir_in[INPUT_LENGTH];
    m_data_t fir_out[OUTPUT_LENGTH];
    m_data_t temp_out[OUTPUT_LENGTH];
    config_t fir_config;
    static hls::FIR<config1> fir1;
    config_t config = 0;
 #pragma HLS dataflow
    for (int i=0; i<3; i++){
  #pragma HLS pipeline rewind
     //config = i;
  #pragma HLS dataflow
  dummy_fe(&in[i*INPUT_LENGTH], fir_in, &config, &fir_config);
  fir_top(fir_in, fir_out, &fir_config);
  for (int j=0; j<OUTPUT_LENGTH; j++){
   #pragma HLS pipeline
   out[i*OUTPUT_LENGTH+j] = temp_out[j];
  }
    }
}
====================================================
The function fir_top() above is the function in the HLS examples, which can be dataflowed separately.
I used the above codes and directives, and cannot get the idea results, in which the data can be put rewind to fir_top() function.

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1 Solution

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Voyager
Voyager
4,973 Views
Registered: ‎06-24-2013

Re: How to pipeline a loop which contains a FIR IP?

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tianzizhou@gmail.com,

 

However, in some design the FIR must be used in a pipeline loop, just as design in my test codes.

Given that the statement in UG902 is true (I'm assuming it is), there is no way to pipeline it. period.

 

And how to resolve the problem!

Despite the misleading exclamation mark, presuming that's a question, here are some options:

  • Try to apply the associated advice (pipelining loops nearby, use dataflow optimization)
  • Implement your own pipelined FIR in case the improvement is not sufficient for your purpose.
  • Pay Xilinx a lot of money to make the FIR pipelineable

Best,

Herbert

-------------- Yes, I do this for fun!
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6 Replies
Voyager
Voyager
3,074 Views
Registered: ‎06-24-2013

Re: How to pipeline a loop which contains a FIR IP?

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Hey tianzizhou@gmail.com,

 

The user guide file UG902 says that the FIR IP cannot be pipelined.

Well, it actually says:

IMPORTANT: The FIR cannot be used in a region which is pipelined. If high-performance operation is required, pipeline the loops or functions before and after the FIR then use dataflow optimization on all loops and functions in the region.

 

Best,

Herbert

-------------- Yes, I do this for fun!
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3,052 Views
Registered: ‎08-22-2017

Re: How to pipeline a loop which contains a FIR IP?

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Thank you, Herbert.
However, in some design the FIR must be used in a pipeline loop, just as design in my test codes. And how to resolve the problem!
0 Kudos
Voyager
Voyager
4,974 Views
Registered: ‎06-24-2013

Re: How to pipeline a loop which contains a FIR IP?

Jump to solution

tianzizhou@gmail.com,

 

However, in some design the FIR must be used in a pipeline loop, just as design in my test codes.

Given that the statement in UG902 is true (I'm assuming it is), there is no way to pipeline it. period.

 

And how to resolve the problem!

Despite the misleading exclamation mark, presuming that's a question, here are some options:

  • Try to apply the associated advice (pipelining loops nearby, use dataflow optimization)
  • Implement your own pipelined FIR in case the improvement is not sufficient for your purpose.
  • Pay Xilinx a lot of money to make the FIR pipelineable

Best,

Herbert

-------------- Yes, I do this for fun!
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3,043 Views
Registered: ‎08-22-2017

Re: How to pipeline a loop which contains a FIR IP?

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your three advices are usefull, especially the second one of writing my own FIR ip.
I think the utility of FIR in a loop is very frequently in design. And the xilinx should give a more useful method to pipeline or dataflow the FIR ip.
And the FFT IP is also has the same problem.
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Scholar u4223374
Scholar
3,029 Views
Registered: ‎04-26-2015

Re: How to pipeline a loop which contains a FIR IP?

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tianzizhou@gmail.com The problem is that "PIPELINE" does instruction-level pipelining - which requires it to unroll every sub-loop. While this is technically possible for something like the FFT block, it's horribly expensive and inefficient.

 

Task-level pipelining is supported in HLS using the DATAFLOW pragma.

 

Alternatively, you can rewrite the FIR/FFT IP yourself in a way that is more pipeline-friendly.

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3,014 Views
Registered: ‎08-22-2017

Re: How to pipeline a loop which contains a FIR IP?

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Thanks! At recently, rewriting the IPs is the best method to improve the performance.
Is there a schedule to improve the pipeline and datadflow directives by Xilinx?
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