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Registered: ‎05-11-2018

How to prevent inferring control signals into FIFOs


Now I have a module like below: 


void top_func(  
    ap_uint<BUS_WIDTH> *in,   // in  , --> m_axi
ap_uint<BUS_WIDTH> *out , // out , --> m_axi
ap_uint<1024> control0 , // control signal0 , configure it once before the kernel running --> s_axilite
ap_uint<1024> control1 // control signal1 , configure it once before the kernel running --> s_axilite
) {
#pragma HLS DATAFLOW ,
sub-funcA ( ... , ... , control0 , control1 ) ;
sub-funcB ( ... , ... , control0 , control1 ) ;
sub-funcC ( ... , ... , control0 , control1 ) ;

And I found that VHLS infer all the control signals into FIFO_w1024_d2 and implement it useing BlockRams. 

what‘s more, these FIFOs had been copied 3 times for 3 sun-functions. ’

That cost many BRAMs . 

My question is why the control signals are inferred into FIFOs ? How to prevent it and  constrain these control signals to save resources. 

Anyone knows the solution?

Thank you .


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1 Reply
Registered: ‎07-18-2018

Re: How to prevent inferring control signals into FIFOs

Hi yanhan


If you want to use Dataflow, you are likely going to need to have three instances of the function. Otherwise those resources will not be able to be run in steps.


From the Xilinx Example Page: https://www.xilinx.com/html_docs/xilinx2018_2/sdaccel_doc/pragma-hls-dataflow-sxx1504034358866.html


In order to take advantage of Data flow, each function will have it's own instance where it can be called in parallel depending on dependencies allowing quicker execution. I don't know the details of your own setup, so this might not be what you expect or are trying at this portion of the design.

As for the interfaces and the BRAM usage, you can tell the FIFO to not use BRAMs with the RESOURCE Directive, and you can use ap_ctrl_none on the interface to tell the tool you don't want additional control signals.


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