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Visitor
Visitor
472 Views
Registered: ‎03-17-2020

How to set the latency what i want in HLS?

I am an FPGA newbie.

I want to ask a very simple question.

 

I want to implement a very simple function that receives axi stream data and outputs the same axi stream data in HLS.

There is no operation to calculate the received data separately, and the received data is output as it is.

This is very easy.

 

 

However, I would like to make the actual input / output cycles differ by an odd number of clocks such as 1, 3, 5, .. etc.

When writing a code that simply reads, stores, and outputs the input of stream data, 2 cycles differ.

I tried using the insert directive function with 2P-RAM, but the result is the same.

How can I make an odd number of clock cycles between input / output?

I'm asking a question because it didn't go well despite trying several methods.

 

 

Regards.

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Xilinx Employee
Xilinx Employee
456 Views
Registered: ‎09-04-2017

@twyu0211  Did you try the latency pragma?

Thanks,

Nithin

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Visitor
Visitor
444 Views
Registered: ‎03-17-2020

Thank you for replying.

 

We set the latency to the desired value using the pragma, and the HLS results are as follows.

However, if you proceed to Vivado Design using the block and observe the data through ILA, it seems that the desired latency is not satisfied.

20200514_211845.png

20200514_211829.png

20200514_211804.png


When observing data with ILA, the goal is to increase the latency of the output data compared to the input by an odd cycle.

 

Any ideas?

 

 

Regards.

 

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Xilinx Employee
Xilinx Employee
441 Views
Registered: ‎09-04-2017

@twyu0211  what do you observe in co-sim?

Thanks,

Nithin

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Visitor
Visitor
434 Views
Registered: ‎03-17-2020

Thank you for replying.

I made the block with desired latency and brought it as an ip on vivado.

 

20200514_213714.png

20200514_211804.png

Experimental setup was done as follows, and the result of updating the bitstream file in the real FPGA was observed by ILA.


Data passing through the ADC is axi stream data, and two pieces of data going through the block are also axi stream data.

The function I want is to delay the digital data coming out of each clock through the ADC by an odd multiple of the clock.

 

Regards.

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Xilinx Employee
Xilinx Employee
421 Views
Registered: ‎09-04-2017

@twyu0211  Did not fully understand your waveform. This is what i would suggest.

Since you developed the desired block in HLS, we have co-sim support in the tool, which can show the cycle accurate behavior. If it shows there properly, then we can see what's causing the diff in hardware.

Since we don't have to go all the way to bitstream, you can quickly run the experiments at co-sim level

Thanks,

Nithin

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Scholar
Scholar
394 Views
Registered: ‎03-28-2016

@twyu0211 ,

You might look at the ap_wait_n() function in ap_utils.h.

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com
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Voyager
Voyager
387 Views
Registered: ‎06-20-2012

It's a simple 2 stages register, do it in RTL.

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