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Registered: ‎09-17-2018

How to set up a manual pipeline / force pipeline stages

Hi experts, 

I'm doing a pipeline design and getting confused by how HLS pipeline works. My design is a simple four-stage pipeline with fetcher, decoder, executer, writeback. And I add pipeline registers in between, naming them FD, DX, XW respectively. 

Fetcher, decoder, executer and finalizer (writeback) is implemented in seperate functions which works well and can be synthesized as expected:Capture.PNG





My top level pipeline defines the instance of stage registers (defined struct) and call these functions like this:

void pipeline (...){
#pragma HLS pipeline static FDreg fd; static DXreg dx; static XWreg xw; static bool halt; Finalizer(&xw, .., .., &halt); //sub-funcs have been pipelined as well Executer(&dx, &xw, ...); Decoder(&fd, &dx, ...); Fetcher(&fd); }

I was hoping these four functions would be fully pipelined and use my defined struct as pipeline registers. So the expected result II should be the longest II among four stages (3 in my case). However, the result turns out to be adding them together as Capture.PNGthe following:


I've tried several primatives including PIPELINE, DATAFLOW, LATENCY, DEPENDENCY. None of these seems to resolve this. Any suggestions or clues are mostly welcomed. Thanks!


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Registered: ‎09-17-2018

Guys, I found a possible solution and this maybe inspiring. I could manually let HLS synthesis a stage Register like this:

void StageRegister(FDReg* in_reg, FDReg* out_reg){
static FDReg local;
*out_reg = local;
local = *in_reg;

This will be synthesised into a seperate module with interface you can define. But this really seems stupid. Should vivado provide ability to add register in HLS or IP integrater directly?

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