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Newbie
Newbie
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Registered: ‎02-21-2020

How to simulate a vivado_hls IP with vivado

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Hello,

I am using vivado (version 2019.1) to synthesize a design that includes an IP generated from vivado_hls, together with manual VHDL files (using a block design in vivado to connect the components)

The synthesis is OK, but I cannot simulate my design, when I run Simulate -> run simulation, I see only the ports of the VHDL file, not the ones of the vivado HLS IP.

How can I include a vivado_HLS IP in  a vivado block design and simulate it in vivado?

Thank you for your help

Tanguy

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Scholar
Scholar
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Registered: ‎03-28-2016

@trisset ,

In the Hierarchy tab of the Source window, open the "Simulation Sources" section and verify that your testbench file is listed as the "Top" module.  If not, select the testbench file, right click the mouse and select "Set as Top".

Your posted image suggests that Vivado has "i2cemu" is specified as the top module for simulation.

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com

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Moderator
Moderator
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Registered: ‎05-27-2018

Hi @trisset ,

     For sure the IP generated by HLS can be simulated in Vivado.

     Are there any logs or screen snaps showing this error? how was the project configuration when you exported the IP in HLS?

Have you added the IP repository correctly?

 

Wen

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Newbie
Newbie
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Registered: ‎02-21-2020

Well, how can I say...

Yes the IP is added correctly because the synthesis and execution on board is working (I have attached the pdf of the block design)

But when I am simulating (Simulation -> run simulation), In the scope window I can only see the i2cemu IP (antoher IP added directly from VHDL), and I cannot see the "Faust_v3" IP which comes from vivado_hls, hence I cannot add the Faust I/O signals to the wave windows

Actually I realize that I do not understand how the components that are proposed in the simulation "scope" window are selected and how they can be changed.

Thanks for your help

Tanguy

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Moderator
Moderator
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Registered: ‎05-27-2018

Hi @trisset ,

      all the modules in block design automatically added into scope when performing the simulation. 

      Could you expand the IP in the resource window and check if you can see all the RTL source files in the HLS IP?

      What's your configuration settings when exporting the IP?

      sim_hls.PNG

Wen

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如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
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Newbie
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Registered: ‎02-21-2020

I could expand the Faust IP (after coming back to the block design, couldn't figure out exactly why, but it finaly worked : see "source.png attached)

But if I switch to "scope" (i.e. see scope.png), I only see the i2cemu and cannot add the faust_v3 source.

the IP was generated with the following script (maybe it is because I commented out the csim_design? but I do not see any relation between simulation in vivado_hls and vivado)

command: vivado_hls -f ../run_hls_v3.tcl

-------------------- file run_hsl_v3.tcl -------------------------------

open_project -reset faust_v3_ip
set_top faust_v3
add_files faust_v3_ip/faust_v3.cpp

open_solution -reset "faust_v3"
set_part {xc7z010clg400-1}
create_clock -period 8

#csim_design
csynth_design
#cosim_design
export_design -rtl vhdl -format ip_catalog

exit

-------------------------------------------------

sources.png
scope.png
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Scholar
Scholar
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Registered: ‎03-28-2016

@trisset ,

In the Hierarchy tab of the Source window, open the "Simulation Sources" section and verify that your testbench file is listed as the "Top" module.  If not, select the testbench file, right click the mouse and select "Set as Top".

Your posted image suggests that Vivado has "i2cemu" is specified as the top module for simulation.

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com

View solution in original post

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Newbie
Newbie
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Registered: ‎02-21-2020
Thanks a lot! it works....
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