How to simulate with C language on SDK in the non-project

[luoxi213]

我通过编写非项目Tcl脚本的示例来完成一个简单的项目，并生成了仿真的Verilog网表文件和用于验证的位流文件。

之后，如何使用C语言文件进行仿真？

[aoifem · Accepted solution]

Hi @luoxi213 

Did you know that we have a Chinese Language Forums?

Our Chinese Language forums have been going strong for more than 2 years, covering all the Xilinx devices, tools, and IP staffed by Xilinx experts with the assistance of the Rising Stars. 

When you have a question to ask in the Chinese Language, please ensure that you only ask the question to the Chinese Community: https://forums.xilinx.com/cn.

两年多来，我们的中文论坛一直在蓬勃发展，涵盖了所有Xilinx的器件，工具，IP等方方面面。我们的专家工程师以及论坛明日之星的成员都会在中文论坛尽力协助您解决问题。

所以如果您有中文问题，请确保仅在中文社区提问，中文论坛网址：https://forums.xilinx.com/cn.

Thank you

[aoifem · Accepted solution]

Our Chinese Language forums have been going strong for more than 2 years, covering all the Xilinx devices, tools, and IP staffed by Xilinx experts with the assistance of the Rising Stars. 

When you have a question to ask in the Chinese Language, please ensure that you only ask the question to the Chinese Community: https://forums.xilinx.com/cn.

两年多来，我们的中文论坛一直在蓬勃发展，涵盖了所有Xilinx的器件，工具，IP等方方面面。我们的专家工程师以及论坛明日之星的成员都会在中文论坛尽力协助您解决问题。

所以如果您有中文问题，请确保仅在中文社区提问，中文论坛网址：https://forums.xilinx.com/cn.

Thank you