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Explorer
Explorer
611 Views
Registered: ‎01-18-2019

How to synthesize a SystemC module (a class declaration)?

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Dear All,

I am trying to make a NAND gate in SystemC  (Vivado 2019.2, Win10) :

SC_MODULE ( nand2_c ) {

	sc_in< sc_int<1> > a, b;
	sc_out< sc_int<1> > f;

	void nand2_main() {
		f.write( !(a.read() & b.read() ) );
	}

	SC_CTOR (nand2_c) {
		SC_METHOD ( nand2_main );
		sensitive << a << b;
	}
};

But this is only a class declaration.

Q1: A testbench can instantiate it into an object,  but how the hack can I synthesize it?  Synthesis is not supposed to rely on testbench files...

Q2: If there were 2 functions, say a NAND and a NEGATE, connected "in series", then what should be set in the "Top Function" textfield?  (Project -> Project Settings ->  Synthesis tab ) ? 

Someone please help!

I am stuck.  Thank you.

Miklos

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Accepted Solutions
Moderator
Moderator
475 Views
Registered: ‎03-16-2017

@mbence76 

i can answer your second query from UG 902 : 

>>Q2: If there were 2 functions, say a NAND and a NEGATE, connected "in series", then what should be set in the "Top Function" textfield?  (Project -> Project Settings ->  Synthesis tab ) ? 

Check page 23.Note section. https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug902-vivado-high-level-synthesis.pdf

systemc.PNG

 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.

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5 Replies
Xilinx Employee
Xilinx Employee
606 Views
Registered: ‎05-22-2018

Hi @mbence76 ,

Please check the below link, might be helpful:

https://www.xilinx.com/products/design-tools/vivado/prod-advantage/rtl-synthesize.html

Thanks,

Raj

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Explorer
Explorer
589 Views
Registered: ‎01-18-2019
Hi Raj,

that link is only about HSL simulation being much faster than RTL. As for the links, I have gone thru all the tutorials and the info I am looking for appearently skipped my eyes. I cannot believe that anyone can use SystemC without knowing the answer to my question. If you do, please write it down for me. Thank you indeeed.
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Explorer
Explorer
526 Views
Registered: ‎01-18-2019

Dear All,

I cannot believe that in this HLS Forum of Xilinx noone knows how to synthesize a very simple SystemC code (a NAND gate) into an RTL description.

The lack of replies makes me think that I must be in some sort of total misconception with my question.

I have been googling for days now and found out many useful stuff about SystemC, but I still cannot synthesize my code.

It must not be so difficult.

Somebody please help!

Miklos

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Moderator
Moderator
476 Views
Registered: ‎03-16-2017

@mbence76 

i can answer your second query from UG 902 : 

>>Q2: If there were 2 functions, say a NAND and a NEGATE, connected "in series", then what should be set in the "Top Function" textfield?  (Project -> Project Settings ->  Synthesis tab ) ? 

Check page 23.Note section. https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug902-vivado-high-level-synthesis.pdf

systemc.PNG

 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.

View solution in original post

Explorer
Explorer
468 Views
Registered: ‎01-18-2019
Wow, hemangd, thank you very much !! That "IMPORTANT!" section in the above picture also explains my other problem, namely why my .h files appear in my Sources folder: Because I added them.. I found no other way to add them, but now I guess all I have to do is place them in the same (windows) folder as the .cpp files.