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fpga_boy
Observer
Observer
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Registered: ‎06-03-2019

I can't use two different hls-generated IPs in vivado at the same time

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I generated two IPines in hls, neither IP compilation nor simulation errors。The simulation results are as follows:微信截图_20190920135645.png

微信截图_20190920135705.png

I take two camera images in vivado at the same time, and then give the images to the resulting hlsIP processing。The problem is that when the image is processed is two of the same IP when there is no problem, using two different IP will be reported error, compilation will not pass.

微信截图_20190920140638.png微信截图_20190920140704.png

The error message reported by the compilation is this:

微信截图_20190920140958.png微信截图_20190920141051.png微信截图_20190920141106.png

Using two identical IPs does not misrepresent and compiles through:

微信截图_20190920141801.png

The version I'm using is vivado 2017.4,The computer system version is win10.

 

 

 

 

 

 

 

 

 

 

 

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wenchen
Moderator
Moderator
774 Views
Registered: ‎05-27-2018

Hi @fpga_boy ,

    In Vivado, click "Generate Block Design" and then select the "Out of context per IP" option. 

    These two HLS IP cores should have used the hls:: AXIvideo2Mat primitive to convert the image data stored in the hls:: Mat format into the hls:: stream format of AXI4 Video stream. If two IPs are integrated as a whole at the same time, the Vivado tool will confuse, because the port data of the invoked HLS IP is defined when the IP core is packaged into RTL, and the modules of both IP ports are Mat2AXIvideo_U0.

    You can open the VHDL/Verilog code of IP in HLS and have a look.

Thanks,

Wen

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wenchen
Moderator
Moderator
775 Views
Registered: ‎05-27-2018

Hi @fpga_boy ,

    In Vivado, click "Generate Block Design" and then select the "Out of context per IP" option. 

    These two HLS IP cores should have used the hls:: AXIvideo2Mat primitive to convert the image data stored in the hls:: Mat format into the hls:: stream format of AXI4 Video stream. If two IPs are integrated as a whole at the same time, the Vivado tool will confuse, because the port data of the invoked HLS IP is defined when the IP core is packaged into RTL, and the modules of both IP ports are Mat2AXIvideo_U0.

    You can open the VHDL/Verilog code of IP in HLS and have a look.

Thanks,

Wen

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.


**~ Got a minute? Answer our Vitis HLS survey here! ~**


-------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------

View solution in original post

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