UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Contributor
Contributor
362 Views
Registered: ‎07-08-2019

Identify an expression implemented by DSP resources in Vivado HLS synthesis

Jump to solution

Hi,

I am implementing a simple convolution using vivado. It contains six nested loops among which I parallelized the two innermost loops as the core of Multiply-and-Accumulate computations.

I expect it to use 105 DSP48E units after implementation. But, it uses 139 DSPs instead.

I checked the synthesis report and I found that VivadoHLS assigns 105 DSPs to multiplier and adder Instances (as I expect) and assigns the rest (34 DSPs) to Expressions.

 

1.png

I checked the expression details, I found that these 34 DSPs are used to implement expressions related to three variables, namely bound1_fu_1288_p2, bound2_fu_1378_p2bound_fu_1275_p2.

 

2.png

 

Is there any way to identify parts of my C++ code corresponding to these variables and/or set them to be implemented by other logic like LUT?

Thanks in advance,

Ali Kokhazadeh

0 Kudos
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
330 Views
Registered: ‎09-04-2017

Re: Identify an expression implemented by DSP resources in Vivado HLS synthesis

Jump to solution

Hi Ali,

  Did you check after Logic Synthesis if the DSP count matches. These are HLS estimates. You can go to Analysis view and try to cross probe from there to see which portion is inferring this one

Thanks,

Nithin

View solution in original post

2 Replies
Xilinx Employee
Xilinx Employee
331 Views
Registered: ‎09-04-2017

Re: Identify an expression implemented by DSP resources in Vivado HLS synthesis

Jump to solution

Hi Ali,

  Did you check after Logic Synthesis if the DSP count matches. These are HLS estimates. You can go to Analysis view and try to cross probe from there to see which portion is inferring this one

Thanks,

Nithin

View solution in original post

Highlighted
Contributor
Contributor
312 Views
Registered: ‎07-08-2019

Re: Identify an expression implemented by DSP resources in Vivado HLS synthesis

Jump to solution

Hi Nithin,

I had not performed Logic Synthesis (Using Export RTL option).

I tried it and found that the resource usage (including DSP usage) is lower than HLS estimates.

 

3.png

 

The DSP usage is 129 (10 units less than HLS estimates). It still uses 24 extra DSPs more than what I expected (i.e., 105). But for now, this overhead is acceptable for my design purpose.

In case of the need for less DSP usage overhead, I will try cross probe in Analysis view.

Thanks a lot,

Ali

0 Kudos