12-07-2015 03:40 AM
I am working on a Board with a extern camera and I want to do some image processing with the opencv libary.
I've a few questions and i hope that you can help me!
1. How are images stored on a FPGA? They cant be stored in a file on the FPGA i think.
2. How do I get these data in the correct form to use the opencv functions? I heard about AXI but im not sure how to use it.
3. I understood the tutorial of 'xapp 1167' and created an own ip core. Do I have to use these in the Block Design? Isn't it possible to use it like a function in verilog code?
4. How can I use ethernet to send the data to a pc after the image processing is done?
5. Are there any useful IP Cores in the IP Catalog I can use (AXI?)?
I'm sorry for my bad English.
I really hope that you can answer some questions!
12-08-2015 01:59 AM
(1) Generally, they're not. For small images and large FPGAs you can afford to buffer a whole frame in block RAM if necessary, but this is really expensive (640x480 image with 8-bit RGB will occupy 400 BRAM_18K blocks if you fit it perfectly, and 450 with the most "straightforward" approach (ie one colour value in each element of a 9-bit block RAM). Even so, this doesn't give you the neat "any pixel, any order" random access that a PC does.
Ideally, you just stream the image. It comes from the camera or external memory one pixel at a time, you process that pixel, and then output it - so you only have to store a single pixel at any time. Realistically, most algorithms require storing at least a few lines of data. This can be easily accomplished with block RAM.
Sometimes it may be necessary to stream the image through twice; first to calculate what you're going to do with it, and then again to actually apply that transformation.
If all else fails, you can just assign the interface as an AXI master, and Vivado will sort out the interfaces necessary to fetch individual pixels from external RAM - but this will be really, really slow.
(2) That depends on your video source. Xilinx provides a Video In to AXI4 Stream IP core, which will probably help most of the time. Once that's done you don't need to think about AXI at all - you just connect the blocks together and Vivado figures out the interface.
(3) The IP core includes Verilog or VHDL code; you can certainly just pull that code out and call the functions directly.
(4) I'm not sure, but Xilinx also provides an AXI to Ethernet core. I'd imagine that you could connect that up to the image output.
(5) See above; the Video In to AXI and AXI to Ethernet cores seem pretty handy.
12-24-2016 06:10 PM
Please refer to this for image processing on FPGA using Verilog:
or this for how to load an image into FPGA for processing: