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davidpeng2017
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Registered: ‎11-12-2018

Initialize FIFO and carried dependence constraint warning

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Hi, all,

In my HLS design, I implement a FIFO for free pointer management. Design is like:

top() {

#pragma HLS DATAFLOW

    hls::stream<T> fifo;

#pragma HLS stream depth=128 variable=fifo

    mod_A(fifo); // FIFO read here

    mod_B(fifo); // FIFO write here

}

But I have no idea on how to initialize the FIFO by property/constraint. So I impl it in mod_B:

mod_B(hls::stream<t> fifo) {

#pragma HLS pipeline II=1

#pragma HLS INLINE off

    switch (state) {

    case INIT_FIFO:

        for (int i=0; i<128; i++) {

            fifo.write(i)

        }

        state = NEXT_STATE;

        break;

    }

    ...

 

Synthesis then report warning in mode_B like:

 WARNING: [SCHED 204-68] The II Violation in module 'mod_B' (Function: mod_B): Unable to enforce a carried dependence constraint (II = 255, distance = 1, offset = 1)
between fifo write on port 'fifo_V_V' (mod_B.cpp:21) and fifo write on port 'fifo_V_V' (mod_B.cpp:21).

Questions:

1. Any better way to initialize the FIFO?

2. actually I don't need HLS to unroll the initialization loop. But as I want to pipeline the whole function, I find no way to disable the unroll for the particular loop.

3. I tried to add #pragma HLS dependence variable=fifo inter false. But the carried dependence warnings are still reported and final II=256.

Thanks in advance,

David

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davidpeng2017
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675 Views
Registered: ‎11-12-2018

I find one way to solve it (work around?)

switch (state) {
case INIT_FIFO:
    fifo.write(init_index);
    init_index++;
    if (init_index < 128) {
        state = INIT_FIFO;
    } else {
        state = RESP_HEADER;
    }
    break;

......

This can get II = 1, at least.

 

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davidpeng2017
Visitor
Visitor
676 Views
Registered: ‎11-12-2018

I find one way to solve it (work around?)

switch (state) {
case INIT_FIFO:
    fifo.write(init_index);
    init_index++;
    if (init_index < 128) {
        state = INIT_FIFO;
    } else {
        state = RESP_HEADER;
    }
    break;

......

This can get II = 1, at least.

 

View solution in original post

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drjohnsmith
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Teacher
660 Views
Registered: ‎07-09-2009

Just a thought ?

   how are you intending the hardware to implement the FIFO that needs initialisation ?

 

 

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davidpeng2017
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Registered: ‎11-12-2018

Dr. Smith,

I design a cache with a free pointer management system.

I initialize a free pointer list (which is a FIFO) with all block addresses. When I need block, I read from the list and write data to the block pointer address. In my process, I use the pointer to access the data. After process, I write the pointer to the FIFO to return it to free pointer list.

Thanks,

David

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drjohnsmith
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Teacher
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Registered: ‎07-09-2009

And is this going to be implemented in the FPGA logic  ?

 

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davidpeng2017
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Registered: ‎11-12-2018

Yes. If i do a pure RTL design, i'll have such list and initialize the list before other logics.

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