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Registered: ‎05-16-2018

Intel Intrinsics SSE2 implementation or alternative via C++ Vivado HLS

I need to import an existing project built in C++ (Visual Studio) to Vivado HLS (for a Kintex Ultrascale fpga). My project heavily relies on Intel Intrinsics SSE2 (_mm_aesenc_si128, _mm_loadu_si128, __m128i, _mm_xor_si128, _mm_aeskeygenassist_si128, _mm_shuffle_epi32 to name a few) for optimizations.


Can I somehow include the intrinsics folder in Vivado HLS to recognize the intrinsic functions/types/etc (C:\Program Files (x86)\Microsoft Visual Studio\2017\Community\VC\Tools\MSVC\14.13.26128\include -- for wmmintrin.h, emmintrin.h, etc)?


Is there an easy way to implement this without painstakingly writing huge chunks of my code over again (possibly helper files to convert these intrinsics to code that can be recognized by Vivado HLS)?


Any suggestions or help is greatly appreciated!

*Note: this is NOT for a Zynq SoC (NEON), specifically for Kintex Ultrascale FPGA

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Registered: ‎05-08-2018



I cannot imagine Intel supporting use of their IP in a Xilinx device.  After all, Xilinx and Intel are competitors.  If the roles were reversed, I know the user agreement only allows Xilinx IP to be used in Xilinx devices.  The exceptions are few (if I recall, only the Aurora interface IP is allowed to be used on a non-Xilinx device).


Best to go ask Intel...


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