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Registered: ‎08-31-2017

Is it possible in HLS to use Time Division Multiplexing or Overclocking the DSP Slices ?

Hi, dear HLS experts,


 I come up with the following question and wanna know if HLS is able to achieve against RTL design. If you have any thoughts, please feel free to share and discuss in the thread. Thanks


Problem Description :

  In RTL design, Time Division Multiplexing or Overclocking are common technique in logic design for high speed resource sharing.

However, I'm curious if the technique fits in HLS world or it is don'ts for HLS since HLS doesn't have clocking concept. Intuitively, it seems not easy to use the TDM methodology in HLS.  You can refer to the following link for detail. 




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Scholar u4223374
Registered: ‎04-26-2015

Re: Is it possible in HLS to use Time Division Multiplexing or Overclocking the DSP Slices ?

@nanson I think you might be able to do this with SystemC. The basic C/C++ side of HLS can only support a single clock, so it can't handle time division multiplexing.


I expect that this is something that Xilinx will implement in the future; it's an area where a fairly small amount of automation could make the tool much more powerful (eg. for the usual 100MHz HLS designs, even a 7-series chip could easily run the block RAM at double-clock or even quadruple-clock, giving something akin to 4-port or 8-port functionality).

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