05-14-2020 04:51 AM
Dear Xilinx experts.
Thank you very much for your excellent best supports.
Is it possible to implement clock generation circuit in FPGA?
If I use asynchronous circuit, can I implement it?
Thank you very much.
05-14-2020 05:27 AM
Hi @chldlrtjd ,
You can use Xilinx IP core clcok generator according to your target device:
05-14-2020 06:02 AM
While it is theoretically possible to generate a clock from a ring oscillator--perhaps running a series of "not" gates around the periphery of the programmable logic, abusing the tools to do something like this is not supported by Vivado. Indeed, I know of no technique within the limitations of the build tools that can actually generate a clock from nothing. (Not that I know everything, but feel free to correct me here if I am wrong.) Every technique I am aware of, to include the one @rshekhaw just mentioned as well as my own more unconventional approach, requires an incoming clock to start from.
05-14-2020 06:32 AM
However, you don't get anything like a constant clock speed. It'll change with temperature, it'll change with each device that you use, it'll probably even change every time you run implementation (unless you force Vivado to always put it in the same place). That makes it impractical to use for any logic, because you can't provide any sensible timing constraints.
A better approach would be to use the configuration clock from the FPGA's internal oscillator, which is available through the STARTUPE2 primitive (as CFGMCLK). It's still not exactly stable, but at least it won't change every time you run implementation.
Of course, the correct solution is to just stick an external oscillator on there.