Is it possible to synthesize a port for multiple functions in hls?
I am developing an IP block for a quadrature encoder in HLS. This design requires two ports, one to count encoder pulses and a second s_axilite port for the software interface. Page 90 of ug902 states "If the function return is also specified as an AXI4-Lite interface all the port in the block-level are grouped into the AXI4-Lite interface". This would correspond to the axi software interface. Does mean that are no directives I can use to synthesize the a 2nd function to count encoder pulses?
firstname.lastname@example.org This is not really possible in HLS. One HLS block represents one top-level HLS function. That function can call sub-functions, but fundamentally the top-level function represents the block that gets built.
You could get something roughly similar by specifying an AXI Stream port for the encoder pulses - but I think in this case you would have to essentially leave the function running continuously. It's not going to be very pretty.
This would be a good candidate for conversion to HDL; it'll probably be easier than writing it in HLS, and you'll get numerous benefits from HDL (eg. cycle-accurate timing, sensible behaviour if a pulse occurs while you're reading a register, etc) that HLS may not allow.