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Visitor
Visitor
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Registered: ‎12-09-2014

Is there a way to instantiate DSP48E2 in Vivado HLS?

Hello, 

I'm using Vivado HLS and I'm having many difficulties for infering correctly the DSP48E2 when only using it as adder (my target device is a Kintex US+). So I would like to know if there is a way to explicitly instantiate the DSP in my C-code?

The pragma and the test equation I'm using for now are: 

#pragma HLS RESOURCE variable=my_result core=AddSub_DSP

my_result=A+B; 

I realized Vivado HLS only infers a DSP48 for certains cases, in fonction of the size of A, B & my_result ! I still do not figure out how it works. For exemple, if A, B & my_result are 22, 24 & 10 bits-size respectively Vivado will infer a DSP. But it will NOT if they are 22, 22 & 10 bits-size respectively. 

My goal is to implement a two 24-bit adder using one DSP, for doing something like that:

my_result1=A1+B1; 

my_result2=A2+B2; 

...is that possible? Is there any way to explicitely instantiate a DSP in order to avoir the troubles for the infering?

 

Thanks in advance

 

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Xilinx Employee
Xilinx Employee
623 Views
Registered: ‎05-22-2018

Hi @xilinxlaura 

Please check this AR# link:

https://www.xilinx.com/support/answers/45518.html

Also Please check page no.167 of below link for a DSP48 example:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug902-vivado-high-level-synthesis.pdf

Thanks,

Raj

 

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