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Registered: ‎07-08-2019

Logic Synthesis Error: Run 'synth_1' has not been launched. Unable to open

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Hi,

I am trying to synthesize C++ designs with Vivado HLS 2019.2.

The C synthesis round succeeds. But, the Logic Synthesis fails for every project (even the simplest ones), reporting the following errors:

ERROR: [Common 17-69] Command failed: Run 'synth_1' has not been launched. Unable to open

ERROR: [HLS 200-478] vivado returned an error child process exited abnormally

For example, when synthesizing the following simple code:

#include <math.h>

float fpadder4(float inA, float inB, float inC, float inD)
{
	#pragma HLS pipeline

	float res = inA + inB + inC + inD;
	return res;
}

The C Synthesis proceeds and reports what I expect. But, when trying to export RTL, it fails. The the full report for both C synthesis and Export RTL is as follows:

Starting C synthesis ...
D:/Xilinx/Vivado/2019.2/bin/vivado_hls.bat D:/HLS/simple_project/solution1/csynth.tcl
INFO: [HLS 200-10] Running 'D:/Xilinx/Vivado/2019.2/bin/unwrapped/win64.o/vivado_hls.exe'
INFO: [HLS 200-10] For user 'user1' on host 'desktop-63in9uj' (Windows NT_amd64 version 6.2) on Sun Jan 05 04:08:38 -0800 2020
INFO: [HLS 200-10] In directory 'D:/HLS'
Sourcing Tcl script 'D:/HLS/simple_project/solution1/csynth.tcl'
INFO: [HLS 200-10] Opening project 'D:/HLS/simple_project'.
INFO: [HLS 200-10] Adding design file 'simple_project/fpadder.cpp' to the project
INFO: [HLS 200-10] Opening solution 'D:/HLS/simple_project/solution1'.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 0ns.
WARNING: [HLS 200-40] Cannot find library 'D:/Xilinx/Vivado/2019.2/common/technology/xilinx/Virtex-7/Virtex-7.lib'.
WARNING: [HLS 200-40] Cannot find library 'xilinx/Virtex-7/Virtex-7'.
INFO: [HLS 200-10] Setting target device to 'xc7vx485t-ffg1157-1' INFO: [SCHED 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints. INFO: [HLS 200-10] Analyzing design file 'simple_project/fpadder.cpp' ... INFO: [HLS 200-111] Finished Linking Time (s): cpu = 00:00:03 ; elapsed = 00:00:11 . Memory (MB): peak = 199.871 ; gain = 108.219 INFO: [HLS 200-111] Finished Checking Pragmas Time (s): cpu = 00:00:03 ; elapsed = 00:00:11 . Memory (MB): peak = 199.871 ; gain = 108.219 INFO: [HLS 200-10] Starting code transformations ... INFO: [HLS 200-111] Finished Standard Transforms Time (s): cpu = 00:00:03 ; elapsed = 00:00:12 . Memory (MB): peak = 199.871 ; gain = 108.219 INFO: [HLS 200-10] Checking synthesizability ... INFO: [HLS 200-111] Finished Checking Synthesizability Time (s): cpu = 00:00:03 ; elapsed = 00:00:12 . Memory (MB): peak = 199.871 ; gain = 108.219 INFO: [HLS 200-111] Finished Pre-synthesis Time (s): cpu = 00:00:03 ; elapsed = 00:00:12 . Memory (MB): peak = 199.871 ; gain = 108.219 INFO: [HLS 200-111] Finished Architecture Synthesis Time (s): cpu = 00:00:03 ; elapsed = 00:00:12 . Memory (MB): peak = 199.871 ; gain = 108.219 INFO: [HLS 200-10] Starting hardware synthesis ... INFO: [HLS 200-10] Synthesizing 'fpadder4' ... INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'fpadder4' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining function 'fpadder4'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 12. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 12.567 seconds; current allocated memory: 108.790 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.133 seconds; current allocated memory: 108.899 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'fpadder4' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-500] Setting interface mode on port 'fpadder4/inA' to 'ap_none'. INFO: [RTGEN 206-500] Setting interface mode on port 'fpadder4/inB' to 'ap_none'. INFO: [RTGEN 206-500] Setting interface mode on port 'fpadder4/inC' to 'ap_none'. INFO: [RTGEN 206-500] Setting interface mode on port 'fpadder4/inD' to 'ap_none'. INFO: [RTGEN 206-500] Setting interface mode on function 'fpadder4' to 'ap_ctrl_hs'. INFO: [SYN 201-210] Renamed object name 'fpadder4_fadd_32ns_32ns_32_4_full_dsp_1' to 'fpadder4_fadd_32nbkb' due to the length limit 20 INFO: [RTGEN 206-100] Generating core module 'fpadder4_fadd_32nbkb': 3 instance(s). INFO: [RTGEN 206-100] Finished creating RTL model for 'fpadder4'. INFO: [HLS 200-111] Elapsed time: 0.205 seconds; current allocated memory: 109.227 MB. INFO: [HLS 200-789] **** Estimated Fmax: 121.68 MHz INFO: [HLS 200-111] Finished generating all RTL models Time (s): cpu = 00:00:05 ; elapsed = 00:00:15 . Memory (MB): peak = 199.871 ; gain = 108.219 INFO: [VHDL 208-304] Generating VHDL RTL for fpadder4. INFO: [VLOG 209-307] Generating Verilog RTL for fpadder4. INFO: [HLS 200-112] Total elapsed time: 14.703 seconds; peak allocated memory: 109.227 MB. Finished C synthesis. Starting export RTL ... D:/Xilinx/Vivado/2019.2/bin/vivado_hls.bat D:/HLS/simple_project/solution1/export.tcl INFO: [HLS 200-10] Running 'D:/Xilinx/Vivado/2019.2/bin/unwrapped/win64.o/vivado_hls.exe' INFO: [HLS 200-10] For user 'user1' on host 'desktop-63in9uj' (Windows NT_amd64 version 6.2) on Sun Jan 05 04:10:37 -0800 2020 INFO: [HLS 200-10] In directory 'D:/HLS' Sourcing Tcl script 'D:/HLS/simple_project/solution1/export.tcl' INFO: [HLS 200-10] Opening project 'D:/HLS/simple_project'. INFO: [HLS 200-10] Opening solution 'D:/HLS/simple_project/solution1'. INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns. INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 0ns. WARNING: [HLS 200-40] Cannot find library 'D:/Xilinx/Vivado/2019.2/common/technology/xilinx/Virtex-7/Virtex-7.lib'. WARNING: [HLS 200-40] Cannot find library 'xilinx/Virtex-7/Virtex-7'. INFO: [HLS 200-10] Setting target device to 'xc7vx485t-ffg1157-1'
INFO: [IMPL 213-8] Exporting RTL as a Vivado IP. ****** Vivado v2019.2 (64-bit) **** SW Build 2700185 on Thu Oct 24 18:46:05 MDT 2019 **** IP Build 2699827 on Thu Oct 24 21:16:38 MDT 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source run_ippack.tcl -notrace create_project: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 442.559 ; gain = 159.047 INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.2/data/ip'. WARNING: [IP_Flow 19-4832] The IP name 'fpadder4_ap_fadd_2_full_dsp_32' you have specified is long. The Windows operating system has path length limitations. It is recommended you use shorter names to reduce the likelihood of issues.
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fpadder4_ap_fadd_2_full_dsp_32'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'fpadder4_ap_fadd_2_full_dsp_32'... INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.2/data/ip'. INFO: [Common 17-206] Exiting Vivado at Sun Jan 5 04:11:00 2020... INFO: [IMPL 213-8] Starting RTL evaluation using Vivado ... D:\HLS\simple_project\solution1\impl\verilog>D:/Xilinx/Vivado/2019.2/bin/vivado -notrace -mode batch -source run_vivado.tcl || exit $? ****** Vivado v2019.2 (64-bit) **** SW Build 2700185 on Thu Oct 24 18:46:05 MDT 2019 **** IP Build 2699827 on Thu Oct 24 21:16:38 MDT 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source run_vivado.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/HLS/simple_project/solution1/impl/ip'. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.2/data/ip'. Wrote : <D:\HLS\simple_project\solution1\impl\verilog\project.srcs\sources_1\bd\bd_0\bd_0.bd> WARNING: [BD 41-927] Following properties on pin /hls_inst/ap_clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning. FREQ_HZ=100000000.0 Wrote : <D:\HLS\simple_project\solution1\impl\verilog\project.srcs\sources_1\bd\bd_0\bd_0.bd> VHDL Output written to : D:/HLS/simple_project/solution1/impl/verilog/project.srcs/sources_1/bd/bd_0/synth/bd_0.v VHDL Output written to : D:/HLS/simple_project/solution1/impl/verilog/project.srcs/sources_1/bd/bd_0/sim/bd_0.v VHDL Output written to : D:/HLS/simple_project/solution1/impl/verilog/project.srcs/sources_1/bd/bd_0/hdl/bd_0_wrapper.v Using BD top: bd_0_wrapper
INFO: [BD 41-1662] The design 'bd_0.bd' is already validated. Therefore parameter propagation will not be re-run. VHDL Output written to : D:/HLS/simple_project/solution1/impl/verilog/project.srcs/sources_1/bd/bd_0/synth/bd_0.v VHDL Output written to : D:/HLS/simple_project/solution1/impl/verilog/project.srcs/sources_1/bd/bd_0/sim/bd_0.v VHDL Output written to : D:/HLS/simple_project/solution1/impl/verilog/project.srcs/sources_1/bd/bd_0/hdl/bd_0_wrapper.v WARNING: [IP_Flow 19-519] IP 'bd_0_hls_inst_0' detected a language mismatch between 'VHDL Simulation Wrapper' and 'Verilog Simulation' output products. Please check with the IP provider to see if this is expected. INFO: [BD 41-1029] Generation completed for the IP Integrator block hls_inst . Exporting to file D:/HLS/simple_project/solution1/impl/verilog/project.srcs/sources_1/bd/bd_0/hw_handoff/bd_0.hwh Generated Block Design Tcl file D:/HLS/simple_project/solution1/impl/verilog/project.srcs/sources_1/bd/bd_0/hw_handoff/bd_0_bd.tcl Generated Hardware Definition File D:/HLS/simple_project/solution1/impl/verilog/project.srcs/sources_1/bd/bd_0/synth/bd_0.hwdef [Sun Jan 5 04:11:21 2020] Launched bd_0_hls_inst_0_synth_1... Run output will be captured here: D:/HLS/simple_project/solution1/impl/verilog/project.runs/bd_0_hls_inst_0_synth_1/runme.log [Sun Jan 5 04:11:21 2020] Launched synth_1... Run output will be captured here: D:/HLS/simple_project/solution1/impl/verilog/project.runs/synth_1/runme.log [Sun Jan 5 04:11:21 2020] Waiting for synth_1 to finish... [Sun Jan 5 04:11:41 2020] synth_1 finished WARNING: [Vivado 12-8222] Failed run(s) : 'bd_0_hls_inst_0_synth_1' wait_on_run: Time (s): cpu = 00:00:00 ; elapsed = 00:00:20 . Memory (MB): peak = 633.367 ; gain = 0.000
ERROR: [Common 17-69] Command failed: Run 'synth_1' has not been launched. Unable to open
INFO: [Common 17-206] Exiting Vivado at Sun Jan 5 04:11:41 2020... ERROR: [HLS 200-478] vivado returned an error child process exited abnormally command 'ap_source' returned error code while executing "source D:/HLS/simple_project/solution1/export.tcl" invoked from within "hls::main D:/HLS/simple_project/solution1/export.tcl" ("uplevel" body line 1) invoked from within "uplevel 1 hls::main {*}$args" (procedure "hls_proc" line 5) invoked from within "hls_proc $argv"
Finished export RTL.

Can anyone tell me what is the problem?

Thanks in advance,

Ali

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Moderator
Moderator
734 Views
Registered: ‎05-31-2017

HI @akokha ,

The reason might be due to that you don't have a valid license or you might be using webpack. Ideally, if you have purchased Vivado license then HLS would come by default.

You might be using the webpack ultrascale device because of which you are able to proceed further. Ideally for Webpack devices license check will not takes place. Virtex 7 devices are not included in the Webpack. Please check page 9 of UG 973 regarding the supported Webpack devices.

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Xilinx Employee
Xilinx Employee
900 Views
Registered: ‎09-04-2017

Hi Ali,

  I am not able to reproduce the issue that you mentioned. Can you look at synth_1/runme.log to see if the tool crashed or errored out.

Also, i see you are running on Windows. Is it possible to run on linux once?

Thanks,

Nithin

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Adventurer
Adventurer
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Registered: ‎07-08-2019

Hi Nithin,

I cannot run in linux at the moment.

I checked synth_1 directory. There is only one synth_1 folder in my design located in the following path:

\solution1\impl\verilog\project.runs\

But there is no log file within it. There is one runme.bat as well as one runme.sh.

Also, there is a folder named bd_0_hls_inst_0_synth_1 in the same directory;

\solution1\impl\verilog\project.runs\bd_0_hls_inst_0_synth_1\

 

This folder contains a runme.log file. The contents of this file is as follows:

 

*** Running vivado
    with args -log bd_0_hls_inst_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source bd_0_hls_inst_0.tcl


****** Vivado v2019.2 (64-bit)
  **** SW Build 2700185 on Thu Oct 24 18:46:05 MDT 2019
  **** IP Build 2699827 on Thu Oct 24 21:16:38 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source bd_0_hls_inst_0.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'd:/HLS/simple_project/solution1/impl/ip'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.2/data/ip'.
Command: synth_design -top bd_0_hls_inst_0 -part xc7vx485tffg1157-1 -directive sdx_optimization_effort_high -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx485t'
WARNING: [Common 17-348] Failed to get the license for feature 'Synthesis' and/or device 'xc7vx485t'. Explanation: The license feature Synthesis could not be found.
Resolution: Check the status of your licenses in the Vivado License Manager. For debug help search Xilinx Support for "Licensing FAQ". 
3 Infos, 1 Warnings, 0 Critical Warnings and 1 Errors encountered.
synth_design failed
ERROR: [Common 17-345] A valid license was not found for feature 'Synthesis' and/or device 'xc7vx485t'. Please run the Vivado License Manager for assistance in determining
which features and devices are licensed for your system.
Resolution: Check the status of your licenses in the Vivado License Manager. For debug help search Xilinx Support for "Licensing FAQ". If you are using a license server, verify that the license server is up and running a version of the xilinx daemon that is compatible with the version of Xilinx software that you are using. Please note that Vivado 2017.3 and later requires upgrading your license server tools to the Flex 11.14.1 tools. Please confirm with your license admin that the correct version of the license server tools are installed.
INFO: [Common 17-206] Exiting Vivado at Sun Jan  5 04:11:35 2020...

 

I must mention that I have selected some type of virtex7 family (i.e. xc7vx485t-ffg1157-1) as my target device and I faced a warning regarding not finding a library for Virtex-7 during C Synthesis process.

You can find the above warning in lines 12 and 13 of the C Synthesis report within my previous post (highlighted with red color)

Thanks,

Ali

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎09-04-2017

Hi Ali,

  You can see there is an ERROR due to license

ERROR: [Common 17-345] A valid license was not found for feature 'Synthesis' and/or device 'xc7vx485t'. Please run the Vivado License Manager for assistance in determining

 

Can you change the part once to ultrascale and rerun?

 

Thanks,

Nithin

 

Highlighted
Adventurer
Adventurer
755 Views
Registered: ‎07-08-2019

Hi Nithin,

I changed the target device and it works well with ultrascale+.

So, the library for virtex7 is missing. Can this error be due to license restriction for virtex-7?

Thanks,

Ali

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Moderator
Moderator
735 Views
Registered: ‎05-31-2017

HI @akokha ,

The reason might be due to that you don't have a valid license or you might be using webpack. Ideally, if you have purchased Vivado license then HLS would come by default.

You might be using the webpack ultrascale device because of which you are able to proceed further. Ideally for Webpack devices license check will not takes place. Virtex 7 devices are not included in the Webpack. Please check page 9 of UG 973 regarding the supported Webpack devices.

View solution in original post