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Observer
Observer
483 Views
Registered: ‎07-10-2018

Low-Pass Single-Pole IIR Filter

I am trying to implement Low-Pass Single-Pole IIR Filter on xc7z020-clg400-2 that works on four samples in each clock cycle. Clock is 8 ns, and I have timing failure. I guess that this is because of store and load of last output value (y_prev in this code). Any idea how to solve this problem?

Stefan 

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Moderator
Moderator
389 Views
Registered: ‎10-04-2011

Hello,

I do not see an issue with this design meeting timing in 2019.1 . In HLS the tools report the following:

hls.jpg

And in Vivado synthesis of the exported design I receive the following:

synthesis.jpg

What version of tools are you using? 

Thank you,
Scott

Observer
Observer
375 Views
Registered: ‎07-10-2018

that's right. Please change 

static const EWMA_ACC_T C0=0.99939;

to any different value   e.g C0=0.97  The value 0.99939 is triky because lots of constatnt values will be equal and HLS will optimize design.

Stefan

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