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joancab
Teacher
Teacher
249 Views
Registered: ‎05-11-2015

Master AXI slave offset bundled with other AXI lite parameters

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It looks like HLS doesn't allow me to bundle a Master AXI offset together with other parameters on an AXI lite port.

Am I doing anything wrong or is not possible (cannot see the problem) to have everything (parameters and master AXI offset) in one port?

 

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randyh
Xilinx Employee
Xilinx Employee
157 Views
Registered: ‎01-04-2013

With config_interface -m_axi_offset=slave the tool wants to create a single s_axilite interface and it wants to call it "control". In the Vitis kernel flow this rule is a hard rule, as XRT requires a single s_axilite interface. In the Vivado IP flow this is still more or less an objective of the tool. In your test case, it seems as though the m_axi offset is something the tool needs to map to the s_axilite "control" interface. 

In your test, when all the bundles are mapped to "ctrl", you are creating a single s_axilite interface that is not "control", so the tool returns an error. When you create a separate m_axi bundle=mem_offset, this is mapped to an s_axilite interface called "control", while the rest of the ports are mapped to the s_axilite interface called "ctrl" as you have requested. I have attached an image of the Synthesis Summary for this last case. 

If you remove the "bundle=" from all your pragmas, then they all get mapped to a single s_axilite interface called "control". 

 

 

 

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image.png
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randyh
Xilinx Employee
Xilinx Employee
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Registered: ‎01-04-2013

It seems like that should work. What are you seeing? 

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joancab
Teacher
Teacher
177 Views
Registered: ‎05-11-2015

Let's take this simple code:

 

#include "stdint.h"
#include "hls_stream.h"

using namespace hls;

void top(	uint32_t p1,
			uint32_t p2,
			uint32_t* mem){
#pragma HLS INTERFACE m_axi port=mem offset=slave bundle=ctrl
#pragma HLS INTERFACE s_axilite port=p2 bundle=ctrl
#pragma HLS INTERFACE s_axilite port=p1 bundle=ctrl
#pragma HLS INTERFACE s_axilite port=return bundle=ctrl

}

 

Where I want a single AXI lite port (ctrl) to command the IP, set p1 and p2 parameters and set the offset of the m_axi port.

I get this error:

 

ERROR: [HLS 214-200] Bundle name conflict happens between interface pragma, possible reason: (1) same with maxi offset=off bundle name; (2) same bundle name between maxi and s_axilite interfaces; (3) same with port name directly; in Function 'top(unsigned int, unsigned int, unsigned int*)' (test/top.cpp:8:0)

 

That helps very little... "between interface pragma" - which ones? Then a series of possible reasons:

(1) shouldn't be as m_axi has not offset=off

(2) seems to indicate is no possible to bundle a m_axi offset with other bundled registers.

(3) makes me doubt about the literacy of those who write these error messages.

 

If I drop the 'bundle' option for the top interface:

#include "stdint.h"
#include "hls_stream.h"

using namespace hls;

void top(	uint32_t p1,
			uint32_t p2,
			uint32_t* mem){
#pragma HLS INTERFACE m_axi port=mem offset=slave bundle=ctrl
#pragma HLS INTERFACE s_axilite port=p2 bundle=ctrl
#pragma HLS INTERFACE s_axilite port=p1 bundle=ctrl
#pragma HLS INTERFACE s_axilite port=return

}

I still get the same error. Apparently, only if I set the m_axi offset to a unique AXI lite port (mem_offset in this case) it synthesizes, for example:

#include "stdint.h"
#include "hls_stream.h"

using namespace hls;

void top(	uint32_t p1,
			uint32_t p2,
			uint32_t* mem){
#pragma HLS INTERFACE m_axi port=mem offset=slave bundle=mem_offset
#pragma HLS INTERFACE s_axilite port=p2 bundle=ctrl
#pragma HLS INTERFACE s_axilite port=p1 bundle=ctrl
#pragma HLS INTERFACE s_axilite port=return bundle=ctrl

	uint32_t i;

	for(i=p1; i<p2; i++)
		mem[i] = i*i;
}

This has been tested with Vivado HLS 2020.2

 

 

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randyh
Xilinx Employee
Xilinx Employee
158 Views
Registered: ‎01-04-2013

With config_interface -m_axi_offset=slave the tool wants to create a single s_axilite interface and it wants to call it "control". In the Vitis kernel flow this rule is a hard rule, as XRT requires a single s_axilite interface. In the Vivado IP flow this is still more or less an objective of the tool. In your test case, it seems as though the m_axi offset is something the tool needs to map to the s_axilite "control" interface. 

In your test, when all the bundles are mapped to "ctrl", you are creating a single s_axilite interface that is not "control", so the tool returns an error. When you create a separate m_axi bundle=mem_offset, this is mapped to an s_axilite interface called "control", while the rest of the ports are mapped to the s_axilite interface called "ctrl" as you have requested. I have attached an image of the Synthesis Summary for this last case. 

If you remove the "bundle=" from all your pragmas, then they all get mapped to a single s_axilite interface called "control". 

 

 

 

View solution in original post

image.png
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randyh
Xilinx Employee
Xilinx Employee
89 Views
Registered: ‎01-04-2013

The error seems to be related to the s_axilite and the m_axi both being assigned to the same bundle, 'ctrl'. The following returns an error. But move the m_axi port to bundle=gmem and there is no error. However, you also need to add the mem port to your s_axilite 'ctrl' interface.

#pragma HLS INTERFACE m_axi port=mem offset=slave bundle=ctrl
//#pragma HLS INTERFACE m_axi port=mem offset=slave bundle=gmem
#pragma HLS INTERFACE s_axilite port=mem bundle=ctrl
#pragma HLS INTERFACE s_axilite port=p2 bundle=ctrl
#pragma HLS INTERFACE s_axilite port=p1 bundle=ctrl
#pragma HLS INTERFACE s_axilite port=return bundle=ctrl

 

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