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Visitor
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Registered: ‎02-19-2013

MatrixCore v1.0 for Vivado HLS is going to take off

The MatrixCore library v1.0 contains several important matrix operation core developed with C++, and specially optimized for Vivado HLS. matrix_cplx_conj matrix_real_trans matrix_cplx_trans matrix_real_add matrix_cplx_add matrix_real_sub matrix_cplx_sub matrix_real_mul matrix_cplx_mul matrix_real_inv matrix_cplx_inv Take "matrix_real_inv" for example, which can deal with very ill-conditioned matrix, it supports fully rolled or pipelined architecture. The former is resource-saving but consumes much more computing time than pipelined one. It has features:

1. arbitrary pipelined architecture controlled by predefined macro and C++ template argument

2. arbitrary integer, fixed-point, float, double data type

3. arbitrary error level controlled by C++ template argument (more precision, more computing time for fully rolled architecture, or more computing resource for fully pipelined architecture)

4. arbitrary dimension controlled by C++ template argument

5. can be easily ported to any other HLS tools, such as Catapult C, Synphony CC, CyberWorkBench, C-2-Silicon Compiler, etc.

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Visitor
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Scenario : Fully Rolled Architecture

Platform : Xilinx KC705 Development Kit

Data Type : Float

Dimension : 16x16

Error Level : ~1e-12 (compared with MATLAB function "inv")

Fmax : ~200MHz

Latency : ~473000tCLK

Throughput : ~473000tCLK

LUT6 : 4924

F/F : 6570

DSP48 : 25

BRAM36 : 16

Power : ~125mW (dynamic)

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Scenario : Fully Pipelined Architecture
Platform : Xilinx KC705 Development Kit
Data Type : Float
Dimension : 16x16
Error Level : ~1e-12 (compared with MATLAB function "inv")
Fmax : ~200MHz
Latency : ~473000tCLK
Throughput : ~31412tCLK
LUT6 : 83839
F/F : 118224
DSP48 : 268
BRAM36 : 263
Power : 1913 mW (dynamic power by vecter-less estimation)

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Registered: ‎02-19-2013

datasheep uploaded

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