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Anonymous
Not applicable
10,207 Views

Native FIFO interface and FIFO generator

I am putting a HLS block with stream in and out between two native fifo, one build with fifo-generator, the other sitting in a DMA unit. As can be seen on the figure I have inverted the fifo "empty"  to make it a "empty_n" and the same for "full_n", things are working,- but for me it seems strange. I am afraid that I have missunderstood something in this "handshaking" or else why haven't xilinx made them compatible ? By the way I dont want to use AXI-streams here! fifo2hls.png

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yenigal
Xilinx Employee
Xilinx Employee
10,179 Views
Registered: ‎02-06-2013

Hi

 

The Fifo and the dma fifo and empty signals are of positive polarity and vivado IPI doesn't change them depending on the other blocks present in the design.

 

As the HLS block has negative polartiy signals you have to take of the inversions and your design  looks fine.

Regards,

Satish

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Anonymous
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But I find it a litle strange that the "standard" definitions for two xilinx blocks (HLS and FIFO-generator) are not having the same "polarity", I know HLS once were a third party product... but !?!?!

 

A sideeffect in the IP-integration is I have to "drag" all the individual lines from source to destination in the bus-bundle my self :-( This clutters the design, for large designs this looks awfull and the chance of getting it wrong is large!

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Anonymous
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9,920 Views

Could anyone with knowledge of HLS please tell me that the "backpressure" between a native fifo (made by FIFO generator) and a HLS block is propagted correctly i.e. full (which need to be inverted) is taken care of in the HLS producer logic ? Or should "almost full" be used ? Or is it better to use AXI-stream in order not to loose data ?

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Anonymous
Not applicable
8,841 Views

I'am invoking this thread again. The way things are connected works fine. But now I have a number of such HLS to native fifo connections.

 

It is time consuming and prone to errors that I have to connect all the signals in the fifo_wr and fifo_rd bus manually and via an inverter.

 

Is there a way in HLS to say that full and empty should not be negated ?

 

or in the fifo-generator to say full and empty should be negated?

 

Or does any one else have a trick ? (I don't want to use axi-streams)

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idptech
Observer
Observer
7,542 Views
Registered: ‎02-10-2011

Yes, I agree.

It must be easy to adjust the FIFO_GENERATOR CORE so it fits direct to the Native HLS FIFO inteface.

Just make a checkbox in the core.

 

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clar
Visitor
Visitor
4,697 Views
Registered: ‎07-24-2015

It's 2016/11 now. Is there any option to change full and empty polarity now?

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gsutter
Contributor
Contributor
647 Views
Registered: ‎10-27-2009

I fully agree with yur coment to add the posibility to change the polarty.

My workaround: change the interface in HLS from ap_fifo to axis. Then use a Axi data FIFO.

Regards, G

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