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rappysaha
Adventurer
Adventurer
4,373 Views
Registered: ‎09-21-2016

Need suggestion to decide the language for HLS

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Hello everyone,

 

I am new in case of HLS. I am trying to build an simple IP for video processing. Actually, Xilinx provide many IPs for image processing algorithm but I want to make my own IP with my algorithm. But, I can not decide which language should I use C/C++/SystemC.

 

At first, I have started with C but all of a sudden I noticed a fact about C. When I am building an IP with C, I can not use multiple clocks. From Xilinx user guide and forum, I came to know that I need to use SystemC for that purpose. So, I am trying to learn about systemC now and obviously I am at beginner's level of systemC.

 

My goal: make a simple IP for video processing where I need AXI interface and multiple clocks.

 

Actually, I need some suggestion, to reach my goal, is systemC is a good approach? Or I should follow another way?

 

If I can decide the language, it will be helpful to learn the other steps.

 

Anyway, any suggestion will be very helpful.

 

Thank you

Rappy Saha

 

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u4223374
Advisor
Advisor
7,382 Views
Registered: ‎04-26-2015

If that's the only situation where you need multiple clocks (ie separate clock for AXI-Lite control bus and the main data input/output bus) then HLS can do that even in C++. Check UG902 (v2016.4) on page 115 for details.

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4 Replies
u4223374
Advisor
Advisor
4,360 Views
Registered: ‎04-26-2015

Well, if you want to use HLS and multiple clocks, that makes your choice really easy: SystemC is the only language that will meet your needs.

 

If you just want multiple clocks, then depending on the project you may find that Verilog or VHDL is a better solution. Both will give you much more control over what gets built. The downside is that you have to exercise much more control over what gets built.

muzaffer
Teacher
Teacher
4,329 Views
Registered: ‎03-31-2012

@rappysaha as a beginner to HLS (or even in general) I  suggest that you not use it to generate IP with multiple clocks. This is not what HLS is for. I am sure in your design there is a data-path block of your video processing which works with a single clock and there is some surrounding block which takes two clocks and does the necessary work to make them work together (synchronization, fifo etc). My suggestion would be to do the video processing block in HLS and the wrapper in RTL. You will leave many a hair on your head as this process avoids pulling them out ;-)

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rappysaha
Adventurer
Adventurer
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Registered: ‎09-21-2016

@muzaffer Thank you for your suggestion.

1.JPG

From this picture, you can see that why I need multiple clocks in my IP. One clock is for data_path (red line) and another is for AXI control (yellow line).

What I understand from your suggestion that I should make the video processing part by HLS. But, how can I add the AXI control part in that IP. Actually, I am not clear about RTL wrapper.

If you may explain this part (any tutorial or design link) little bit more, it will be very helpful to me.

 

Thank you

Rappy saha   

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u4223374
Advisor
Advisor
7,383 Views
Registered: ‎04-26-2015

If that's the only situation where you need multiple clocks (ie separate clock for AXI-Lite control bus and the main data input/output bus) then HLS can do that even in C++. Check UG902 (v2016.4) on page 115 for details.

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