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Observer ans.khalid
Observer
343 Views
Registered: ‎03-12-2019

Negative Slack affect and How to Remove

HI,

I am new to vivado HLS. When I try to optimize my design using Optimization directives I am able to reduce latency , but I also get negative slack.

My question is how negative slack affects the design ? should I try to remove this negative slack ? will the IP work when I export it to Vivado HLx and run on FPGA ?

I have tried doing C/RTL co simulation on vivado HLS and it works fine. Does it mean exported IP will work accordingly.

 

If negative slack have some serious affect on the design then how can I remove it ?

Attached screen shot from the analysis pain is also attached.

analysis.PNG
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3 Replies
Moderator
Moderator
308 Views
Registered: ‎03-16-2017

Re: Negative Slack affect and How to Remove

Hi @ans.khalid ,

Note from UG 902 : Vivado HLS estimates the timing and area resources based on built-in libraries for each FPGA. When
you use logic synthesis to compile the RTL into a gate-level implementation, perform physical placement of
the gates in the FPGA, and perform routing of the inter-connections between gates, logic synthesis might
make additional optimizations that change the Vivado HLS estimates

Check on Vivado HLx that you see the negative slack or not after implementation phase (P&R).

 

 

Regards,
hemangd

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Scholar dpaul24
Scholar
295 Views
Registered: ‎08-07-2014

Re: Negative Slack affect and How to Remove

@ans.khalid,

I have tried doing C/RTL co simulation on vivado HLS and it works fine. Does it mean exported IP will work accordingly.

The IP might work at room temp, but not properly at high an dlow temp.

If negative slack have some serious affect on the design then how can I remove it ?

You have to work with timing analysis and constraining the design. You have analyze the failing path and re-work with RTL.

 

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FPGA enthusiast!
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Observer nikhilghanathe
Observer
266 Views
Registered: ‎12-28-2014

Re: Negative Slack affect and How to Remove

Hi,

As @hemangd pointed out, these timing violations might not even be present when you run implementation in Vivado. I have encountered many such as a deigner where these violations just vanish when you run implementation. Bear in mind that the numbers reported by HLS tool is based on software models and hence are conservative more often than not. So you still have some amount of manoeuvring space.

If not, you can try decreasing the target clock frequency and include more pipeline registers in your design (the usual Static timing analysis stuff) to improve the timing of your design.

 

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