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sims
Visitor
Visitor
285 Views
Registered: ‎04-07-2021

Newb trying to get streams to work

Hi,

I'm a software developer trying to figure out how to use FPGA's via PYNQ. I have very little knowledge about actual hardware configuration, as I'm part of a project trying to figure out if PYNQ can enable Data Scientists to accelerate their functions with FPGA's.

I am therefore trying to make a custom overlay which handles streams. To do this, I am trying to mimic the methods of this research paper.

https://www.researchgate.net/publication/337030249_PYNQ-Torch_a_framework_to_develop_PyTorch_accelerators_on_the_PYNQ_platform

Thus, I have ended up with below code in HLS, which I have synthesized and exported the RTL.

sims_0-1617781028482.png

However, when I try to connect my output to the DMA S_AXIS_S2MM port, it cannot connect:

 

sims_1-1617781408641.png

Would anyone be able to assist with this? It would be much appreciated.

 

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3 Replies
randyh
Xilinx Employee
Xilinx Employee
234 Views
Registered: ‎01-04-2013

I recreated your example, and was able to manually connect the output_r to S_AXIS_S2MM. Are you able to do that? 

Here is some additional information related to the AXIS interface:

https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/managing_interface_synthesis.html#doq1539734222381

https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/hls_stream_library.html#mes1539734221433

 

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sims
Visitor
Visitor
177 Views
Registered: ‎04-07-2021

Unfortunately, I am not able to manually connect the output_r to S_AXIS_S2MM, it shows only M_AXIS_MMS2 as a viable interface.

sims_1-1617955151419.png

 

I will try to read the documentation you sent, to see if there's anything which might help me.

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randyh
Xilinx Employee
Xilinx Employee
158 Views
Registered: ‎01-04-2013

It looks like your output port is getting generated as an input, though I am not sure why. What version are you working with? 

 

my_top_func.png
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