04-07-2021 12:44 AM - edited 04-07-2021 01:00 AM
I'm a software developer trying to figure out how to use FPGA's via PYNQ. I have very little knowledge about actual hardware configuration, as I'm part of a project trying to figure out if PYNQ can enable Data Scientists to accelerate their functions with FPGA's.
I am therefore trying to make a custom overlay which handles streams. To do this, I am trying to mimic the methods of this research paper.
Thus, I have ended up with below code in HLS, which I have synthesized and exported the RTL.
However, when I try to connect my output to the DMA S_AXIS_S2MM port, it cannot connect:
Would anyone be able to assist with this? It would be much appreciated.
04-07-2021 10:42 AM
I recreated your example, and was able to manually connect the output_r to S_AXIS_S2MM. Are you able to do that?
Here is some additional information related to the AXIS interface:
04-09-2021 01:00 AM
Unfortunately, I am not able to manually connect the output_r to S_AXIS_S2MM, it shows only M_AXIS_MMS2 as a viable interface.
I will try to read the documentation you sent, to see if there's anything which might help me.
04-09-2021 07:59 AM - edited 04-09-2021 09:26 AM
It looks like your output port is getting generated as an input, though I am not sure why. What version are you working with?