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Visitor zslwyuan
Visitor
617 Views
Registered: ‎01-12-2018

No Ouput in HLS FIFO Interface of Simple Code

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Dear all,

 

    Hi! I am trying to generate signals into a fifo with the following very simple code:

===================

void InGenBlock_1(int output[2000])
{
#pragma HLS INTERFACE ap_fifo port=output
    int i,a,b;
    for (i=0;i<2000;i++)
    {
        output[i] = i;
    }
}

===================

    Accordingly, I build a project including the generated HLS IP Core as shown below:

   

Screenshot from 2019-01-16 23-32-53.png    ================================

        And then I do the behavioral simulation but get nothing in the output port of data, with following Tcl script. The simulation result is also shown below:

add_force {/design_1_wrapper/output_r_full_n_0} -radix hex {0 0ns}
add_force {/design_1_wrapper/sys_clock} -radix hex {1 0ns} {0 5000ps} -repeat_every 10000ps
add_force {/design_1_wrapper/ap_start_0} -radix hex {0 0ns}
add_force {/design_1_wrapper/reset_rtl} -radix hex {1 0ns}
run 10 us
add_force {/design_1_wrapper/reset_rtl} -radix hex {0 0ns}
run 10 us
add_force {/design_1_wrapper/ap_start_0} -radix hex {1 0ns}
run 10 us

        Screenshot from 2019-01-16 23-38-42.png

 ==========================

      When I try the conventional ap_memory interface, there are available outputs. I am confused whether there is any inappropriate in my code or configuration?

      THANKS A LOT in advance for your time and suggestions!

 

Best regards,

-------------------------------

Tingyuan

 

 

 

 

 

0 Kudos
1 Solution

Accepted Solutions
Visitor zslwyuan
Visitor
568 Views
Registered: ‎01-12-2018

Re: No Ouput in HLS FIFO Interface of Simple Code

Jump to solution

@evant_nq

@xilinxacct

Dear all,

 

    Thanks for your time!! I have found the solution here: https://forums.xilinx.com/t5/Vivado-High-Level-Synthesis-HLS/HLS-Integrator-fifo-interface/td-p/847004

    0-0 Interesting HLS....

    Thanks a lot!!

 

Best regards,

-------------------------------------------

Tingyuan

 

5 Replies
Teacher xilinxacct
Teacher
607 Views
Registered: ‎10-23-2018

Re: No Ouput in HLS FIFO Interface of Simple Code

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@zslwyuan

Have you tried hls::stream instead of an array? These natural lend themselves to FIFOs.

Hope that helps

If so, please mark as solution accepted. Kudos also welcomed.

Explorer
Explorer
589 Views
Registered: ‎07-18-2018

Re: No Ouput in HLS FIFO Interface of Simple Code

Jump to solution

What happens if you reduce the array size to 10?

Make it smaller just as a good practice when something doesn't seem to be working properly. Makes the simulation easier to follow.

 

But a quick bit of math, it looks like your clock period is 10ns (10,000ps) That's 100Mhz

You start the block for 10us, which is 10,000ns. 10,000/10 = 1000 clock cycles.

I would confirm it's running for the full 2000 cycles. If you see the latency it takes 2001 cycles for the output, so i suspect that might be what's happening in the simulation.

Highlighted
Visitor zslwyuan
Visitor
572 Views
Registered: ‎01-12-2018

Re: No Ouput in HLS FIFO Interface of Simple Code

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@xilinxacct

Thanks a lot for your suggestion! However, it does not work.

I wonder whether there is any difference between FIFO and STREAM? Or maybe can you point out the problem in the source code?

I wonder whether there is any successful standalone HLS example with FIFO?

Thanks again for your time!

 

Best regards,

--------------

Tingyuan

0 Kudos
Visitor zslwyuan
Visitor
569 Views
Registered: ‎01-12-2018

Re: No Ouput in HLS FIFO Interface of Simple Code

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@evant_nq

Dear Evant,

    Thanks for your suggestions and I have tried all of them but sadly, they still do not work.

    Is there any problem in my source code or could you provide a similar example that works successfully?

    Thanks again for your time!

 

Best regards,

--------------------------------------

Tingyuan

0 Kudos
Visitor zslwyuan
Visitor
569 Views
Registered: ‎01-12-2018

Re: No Ouput in HLS FIFO Interface of Simple Code

Jump to solution

@evant_nq

@xilinxacct

Dear all,

 

    Thanks for your time!! I have found the solution here: https://forums.xilinx.com/t5/Vivado-High-Level-Synthesis-HLS/HLS-Integrator-fifo-interface/td-p/847004

    0-0 Interesting HLS....

    Thanks a lot!!

 

Best regards,

-------------------------------------------

Tingyuan