I am actually working on neural network implementation on Zynq FPGA and I am going with Vivado HLS using OpenCL. I am totally new to OpenCL and a bit confused with how to write host code for the OpenCL kernel. Can anyone help me with this or suggest any resources?
The standalone HLS tool itself does not support the use of OpenCL sources directly. The SDx tools have additional features which allow them to support OpenCL which in turn is synthesized into the kernels using HLS behind the scenes.
The answer to your question depends on what you are doing. If building an embedded system with a co-processor IP in the fabric, then you would want SDSoc. If using a FPGA accelerator board, and accelerating a function used by the host computer, then you would use SDAccel. These tools have tutorials to follow that would answer your question.